$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm 원문보기

IEEE access : practical research, open solutions, v.8, 2020년, pp.149984 - 149998  

Song, Taigon (School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea)

Abstract AI-Helper 아이콘AI-Helper

The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compar...

참고문헌 (44)

  1. Courtland, Rachel. The molten tin solution. IEEE spectrum, vol.53, no.11, 28-41.

  2. Kilpi, O.‐P., Hellenbrand, M., Svensson, J., Lind, E., Wernersson, L.‐E.. Vertical nanowire III-V MOSFETs with improved high‐frequency gain. Electronics letters, vol.56, no.13, 669-671.

  3. 10.1109/ICRAMET.2018.8683936 

  4. 10.1109/IITC-AMC.2017.7968983 

  5. 10.1109/ICICDT.2015.7165874 

  6. Song, Taigon. Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm. IEEE transactions on nanotechnology, vol.18, 240-251.

  7. 10.1109/VLSIT.2016.7573409 

  8. Synopsys Quickcap NX 2018 

  9. 10.1109/IEDM.2017.8268473 

  10. PDK 45nm Open Cell Library 2011 

  11. Metrology Challenges for Gate-All-Around 2020 

  12. 10.1109/DRC.2014.6872333 

  13. Lu, Wei, Xie, Ping, Lieber, Charles M.. Nanowire Transistor Performance Limits and Applications. IEEE transactions on electron devices, vol.55, no.11, 2859-2876.

  14. Lu, Wei, Lieber, Charles M. Semiconductor nanowires. Journal of physics. D, applied physics, vol.39, no.21, R387-R406.

  15. Morales, Alfredo M., Lieber, Charles M.. A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires. Science, vol.279, no.5348, 208-211.

  16. Wu, Y., Cui, Y., Huynh, L., Barrelet, C. J., Bell, D. C., Lieber, C. M.. Controlled Growth and Structures of Molecular-Scale Silicon Nanowires. Nano letters : a journal dedicated to nanoscience and nanotechnology, vol.4, no.3, 433-436.

  17. Int Conf on IC Design and Technology (ICICDT) Lateral NWFET optimization for beyond 7nm nodes yakimets 2015 1 

  18. IBM Research Alliance Builds New Transistor for 5 nm Technology 2017 

  19. VLSI Symp Tech Dig 5 nm-gate nanowire FinFET yang 2004 196 

  20. 10.23919/VLSIT.2017.7998183 

  21. Symp VLSI Technol Dig Tech Papers A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance lee 2004 200 

  22. Trong Huynh-Bao, Sakhare, Sushil, Yakimets, Dmitry, Ryckaert, Julien, Thean, Aaron Voon-Yew, Mercha, Abdelkarim, Verkest, Diederik, Wambacq, Piet. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs. IEEE transactions on electron devices, vol.63, no.2, 643-651.

  23. Samsung Starts Mass Production of Chips Using Its 7 nm EUV Process Tech 2018 

  24. Proc Euro Solid-State Device Res Conf (ESSDERC) Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5 nm and beyond technologies bao 2014 102 

  25. TSMC’s 7nm Technology 2018 

  26. Proc IEEE Electron Devices Technol Manuf Conf (EDTM) FinFET/nanowire design for 5 nm/3 nm technology nodes: Channel cladding and introducing a ‘bottleneck’ shape to remove performance bottleneck moroz 2017 67 

  27. 10.1109/IMW.2011.5873204 

  28. INTEL's Revolutionary 22-nm Transistor Technology 2011 

  29. Symp VLSI Technol Dig Tech Papers Sub-5nm all-around gate FinFET for ultimate scaling lee 2006 58 

  30. Proc Simulation Semiconductor Processes and Devices (SISPAD) Power-performance-area engineering of 5 nm nanowire library cells moroz 2015 433 

  31. 10.1109/IEDM.2007.4418914 

  32. Limited EUV Manufacturing in 2019 2019 

  33. Electronics Cramming more components onto integrated circuits moore 1965 38 114 

  34. 10.1109/IEDM.2008.4796805 

  35. 10.1109/S3S.2015.7333521 

  36. Feng, Peijie, Song, Seung-Chul, Nallapati, Giri, Zhu, John, Bao, Jerry, Moroz, Victor, Choi, Munkang, Lin, Xi-Wei, Lu, Qiang, Colombeau, Benjamin, Breil, Nicolas, Chudzik, Michael, Chidambaram, Chidi. Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.38, no.12, 1657-1660.

  37. Moore, Samuel K.. EUV lithography finally ready for fabs. IEEE spectrum, vol.55, no.1, 46-48.

  38. 10.1109/IEDM.2013.6724557 

  39. 10.1109/IITC.2018.8454841 

  40. Samsung Electronics’ Leadership in Advanced Foundry Technology Showcased With Latest Silicon Innovations and Ecosystem Platform 2019 

  41. Fruchterman, Thomas M. J., Reingold, Edward M.. Graph drawing by force‐directed placement. Software: practice & experience, vol.21, no.11, 1129-1164.

  42. Wenjie Lu, Xin Zhao, Dongsung Choi, El Kazzi, Salim, del Alamo, Jesus A.. Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.38, no.5, 548-551.

  43. CoRR Spring embedders and force directed graph drawing algorithms kobourov 2012 abs 1201s 3011 

  44. Yin, Xiaogen, Yang, H., Xie, L., Ai, X. Z., Zhang, Y. B., Jia, K. P., Wu, Z. H., Ma, X. L., Zhang, Q. Z., Mao, S. J., Xiang, J. J., Zhang, Yongkui, Gao, J. F., He, X. B., Bai, G. B., Lu, Y. H., Zhou, N., Kong, Z. Z., Zhang, Y., Zhao, J., Ma, S. S., Xuan, Z. H., Zhu, Huilong, Li, Y. Y., Li, L., Zhang, Q. H., Han, J. H., Chen, R. L., Qu, Y., Yang, T., Luo, J., Li, J. F., Yin, H. X., Wang, G. L., Radamson, H., Zhao, C., Wang, W. W., Ye, T. C., Li, J. J., Du, A.Y., Li, C., Zhao, L. H., Huang, W. X.. Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.41, no.1, 8-11.

LOADING...

관련 콘텐츠

오픈액세스(OA) 유형

GOLD

오픈액세스 학술지에 출판된 논문

유발과제정보 저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로