[논문]Power Line Interference Reduction Technique with a Current-Reused Current-Feedback Instrumentation Amplifier for ECG Recording

You, Donggeun; Heo, Hyunwoo; Kim, Hyungseup; Kwon, Yongsu; Lee, Sangmin; Ko, Hyoungho

doi:10.3390/app10238478

[해외논문] Power Line Interference Reduction Technique with a Current-Reused Current-Feedback Instrumentation Amplifier for ECG Recording 원문보기

Applied sciences, v.10 no.23, 2020년, pp.8478 -

You, Donggeun (Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea) , Heo, Hyunwoo (Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea) , Kim, Hyungseup (Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea) , Kwon, Yongsu (Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea) , Lee, Sangmin (Department of Biomedical Engineering, Kyung Hee University, Yongin 17104, Korea) , Ko, Hyoungho (Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea)

Abstract ▼ AI-Helper

This paper presents a power line interference (PLI) reduction technique with a current-reused current-feedback instrumentation amplifier (CFIA) for electrocardiogram (ECG) recording. In a portable two-electrode ECG monitoring application, the presence of undesired PLI may severely corrupt the quality of ECG recording. Since PLI can be over a few volts, the input signal including the ECG signal can exceed the supply or ground level by an electrostatic discharge (ESD) diode in input/output (I/O) pad. To prevent this problem, this paper presents a continuous-time input common-mode current feedback loop that can limit displacement current from a capacitive coupling between the human body and a power line. The continuous-time input common-mode current feedback loop can clamp an input common-mode voltage to the saturation region of the input transistor of the current-reused CFIA. After the clamping procedure, the clamped input signal is amplified by the current-reused CFIA. The proposed circuit was designed using a 0.18-μm bipolar-complementary metal semiconductor-double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 1.8 mm2. The total power consumption is 18 μW with 1.8 V. The input-referred noise and noise efficiency factor (NEF) of the current-reused CFIA is 2.68 μVRMS and 4.28 with 107 Hz, respectively.

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