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NTIS 바로가기IEEE journal of solid-state circuits, v.56 no.9, 2021년, pp.2691 - 2700
Chang, Dong-Jin (Korea Advanced Institute of Science and Technology, School of Electrical Engineering, Daejeon, South Korea) , Choi, Michael (Samsung Electronics, Hwaseong, South Korea) , Ryu, Seung-Tak (Korea Advanced Institute of Science and Technology, School of Electrical Engineering, Daejeon, South Korea)
This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular co...
Lin, Chin-Yu, Wei, Yen-Hsin, Lee, Tai-Cheng. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE journal of solid-state circuits, vol.53, no.5, 1508-1517.
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Harpe, P. J. A., Zhou, C., Yu Bi, van der Meijs, N. P., Xiaoyan Wang, Philips, K., Dolmans, G., de Groot, H..
A 26
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Seo, Min-Jae, Roh, Yi-Ju, Chang, Dong-Jin, Kim, Wan, Kim, Ye-Dam, Ryu, Seung-Tak. A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, vol.65, no.12, 1904-1908.
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Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chuin Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee.
A 0.003 mm
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