$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[해외논문] A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

IEEE journal of solid-state circuits, v.56 no.9, 2021년, pp.2691 - 2700  

Chang, Dong-Jin (Korea Advanced Institute of Science and Technology, School of Electrical Engineering, Daejeon, South Korea) ,  Choi, Michael (Samsung Electronics, Hwaseong, South Korea) ,  Ryu, Seung-Tak (Korea Advanced Institute of Science and Technology, School of Electrical Engineering, Daejeon, South Korea)

Abstract AI-Helper 아이콘AI-Helper

This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular co...

참고문헌 (29)

  1. Lin, Chin-Yu, Wei, Yen-Hsin, Lee, Tai-Cheng. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE journal of solid-state circuits, vol.53, no.5, 1508-1517.

  2. Proc Symp VLSI Circuits A 0.014 mm2 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration luo 2017 278 

  3. Proc IEEE Symp VLSI Circuits (VLSI-Circuits) A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS lin 2016 1 

  4. Guo, Mingqiang, Mao, Jiaji, Sin, Sai-Weng, Wei, Hegong, Martins, Rui P.. A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. IEEE access : practical research, open solutions, vol.8, 138944-138954.

  5. Guo, Mingqiang, Mao, Jiaji, Sin, Sai-Weng, Wei, Hegong, Martins, Rui P.. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. IEEE journal of solid-state circuits, vol.55, no.3, 693-705.

  6. Kang, Hyun-Wook, Hong, Hyeok-Ki, Kim, Wan, Ryu, Seung-Tak. A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme. IEEE journal of solid-state circuits, vol.53, no.9, 2584-2594.

  7. Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu. A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, vol.63, no.6, 518-522.

  8. 10.1109/ISSCC.2002.992988 

  9. IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 40 GS/s 6b ADC in 65 nm CMOS greshishchev 2010 390 

  10. 10.1109/ISSCC.2014.6757481 

  11. IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET kull 2017 474 

  12. Harpe, P. J. A., Zhou, C., Yu Bi, van der Meijs, N. P., Xiaoyan Wang, Philips, K., Dolmans, G., de Groot, H.. A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios. IEEE journal of solid-state circuits, vol.46, no.7, 1585-1595.

  13. ISSCC Dig Tech Papers A double-tail latch-type voltage sense amplifier with 18ps setup+hold time schinkel 2007 314 

  14. McCreary, J.L., Gray, P.R.. All-MOS charge redistribution analog-to-digital conversion techniques. I. IEEE journal of solid-state circuits, vol.10, no.6, 371-379.

  15. Sunghyuk Lee, Chandrakasan, Anantha P., Hae-Seung Lee. A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. IEEE journal of solid-state circuits, vol.49, no.12, 2846-2856.

  16. Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Choi, Michael, Ho-Jin Park, Seung-Tak Ryu. A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. IEEE journal of solid-state circuits, vol.50, no.2, 543-555.

  17. Stepanovic, Dušan, Nikolic, Borivoje. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS. IEEE journal of solid-state circuits, vol.48, no.4, 971-982.

  18. 10.1109/ISSCC.2014.6757481 

  19. IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers 26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS sung 2015 464 

  20. Doris, Kostas, Janssen, Erwin, Nani, Claudio, Zanikopoulos, Athon, van der Weide, Gerard. A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. IEEE journal of solid-state circuits, vol.46, no.12, 2821-2833.

  21. Jeonggoo Song, Ragab, Kareem, Xiyuan Tang, Nan Sun. A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. IEEE journal of solid-state circuits, vol.52, no.10, 2563-2575.

  22. Chen, S.-W.M., Brodersen, R.W.. A Subsampling Radio Architecture for Ultrawideband Communications. IEEE transactions on signal processing : a publication of the IEEE Signal Processing Society, vol.55, no.10, 5018-5031.

  23. Zhou, Yuan, Xu, Benwei, Chiu, Yun. A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE journal of solid-state circuits, vol.54, no.8, 2207-2218.

  24. IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 0.85 fJ/conversionstep 10 b 200 kS/s subranging SAR ADC in 40 nm CMOS tai 2014 196 

  25. Moon, Kyoung-Jun, Oh, Dong-Ryeol, Choi, Michael, Ryu, Seung-Tak. A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, vol.67, no.12, 2843-2847.

  26. Seo, Min-Jae, Roh, Yi-Ju, Chang, Dong-Jin, Kim, Wan, Kim, Ye-Dam, Ryu, Seung-Tak. A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, vol.65, no.12, 1904-1908.

  27. Andreani, P., Bigongiari, F., Roncella, R., Saletti, R., Terreni, P.. Digitally controlled shunt capacitor CMOS delay line. Analog integrated circuits and signal processing, vol.18, no.1, 89-96.

  28. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE journal of solid-state circuits, vol.45, no.4, 731-740.

  29. Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chuin Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee. A 0.003 mm $^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. IEEE journal of solid-state circuits, vol.50, no.6, 1382-1398.

LOADING...

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 논문

해당 논문의 주제분야에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

유발과제정보 저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로