[논문]A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock

Yang, Isaak; Cho, Kwang-Hyun

doi:10.1109/tvlsi.2020.3046099

[해외논문] A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock

IEEE transactions on very large scale integration (VLSI) systems, v.29 no.3, 2021년, pp.512 - 518

Yang, Isaak (Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea) , Cho, Kwang-Hyun (Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea)

Abstract ▼ AI-Helper

Timing error is now getting increased attention due to the high rate of error-occurrence on semiconductors. Even slight external disturbance can threaten the timing margin between successive clocks since the latest semiconductor operates with high frequency and small supply voltage. To deal with a timing error, many techniques have been introduced. Nevertheless, existing methods that mitigate a timing error mostly have time-delaying mechanisms and too complex operation, resulting in a timing problem on clock-based systems and hardware overhead. In this article, we propose a novel timing-error-tolerant method that can correct a timing error instantly through a simple mechanism. By modifying a clock in a flip-flop, the proposed system can recover a timing error without the loss of time in the clock-based system. Furthermore, due to the compact mechanism, the proposed system has low hardware overhead in comparison with existing timing-error-tolerant systems that can recover the error instantly. To verify our method, the proposed circuit was extensively simulated by addressing PVT variations. Moreover, it was implemented in several benchmark designs, including a microprocessor.

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DOI : 10.1109/TVLSI.2020.3046099
IEEE : 저널 > 논문

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