[논문]High‐Performance and High‐Endurance HfO2‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Kim, Taeho; Hwang, Junghyeon; Kim, Giuk; Jung, Minhyun; Jeon, Sanghun

doi:10.1002/pssr.202100018

[해외논문] High‐Performance and High‐Endurance HfO2‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Physica status solidi. PSS-RRL. Rapid Research Letters, v.15 no.5, 2021년, pp.2100018 -

Kim, Taeho (School of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Yuseong-gu Daejeon 34141 Republic of Korea) , Hwang, Junghyeon (School of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Yuseong-gu Daejeon 34141 Republic of Korea) , Kim, Giuk (School of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Yuseong-gu Daejeon 34141 Republic of Korea) , Jung, Minhyun (School of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Yuseong-gu Daejeon 34141 Republic of Korea) , Jeon, Sanghun (School of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Yuseong-gu Daejeon 34141 Republic of Korea)

Abstract ▼ AI-Helper

Owing to their high scalability and superior complementary metal-oxide-semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal-ferroelectric-insulator-semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to <106 cycles. Herein, optimum condition of switching polarization () of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with , and a metal-ferroelectric-metal-insulator-semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

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