참고문헌 (23)

1. Colinge 2008 

2. Microelectron. Eng. Colinge 10.1016/j.mee.2007.04.038 84 2071 2007 Multi-gate SOI MOSFETs 

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3. IEEE Trans. Electron Devices Kuhn 10.1109/TED.2012.2193129 59 1813 2012 Considerations for ultimate CMOS scaling 

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4. IEEE Electron Device Lett. Choi 10.1109/55.974801 23 25 2002 Nanoscale CMOS spacer FinFET for the terabit era 

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5. J. Phys. Chem. B Choi 10.1021/jp0222649 107 3340 2003 Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography 

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6. 2017 

7. IEEE Electron Device Lett. Sachid 10.1109/LED.2016.2572664 37 835 2016 FinFET with high-κ spacers for improved drive current 

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8. IEEE Electron Device Lett. Gundapaneni 10.1109/LED.2011.2162309 32 1325 2011 Enhanced electrostatic integrity of short-channel junctionless transistor with high-κ spacers 

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9. IEEE Access Sahay 10.1109/ACCESS.2017.2751518 5 18918 2017 Comprehensive analysis of gate-induced drain leakage in emerging FET architectures: nanotube FETs versus nanowire FETs 

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10. Japan. J. Appl. Phys. Hong 10.7567/JJAP.54.04DN05 54 04DN05 2015 Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs 

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11. IEEE Trans. Electron Devices Hur 10.1109/TED.2017.2757260 64 5223 2017 Schottky tunneling effects in a tunnel FET 

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12. IEEE Trans. Nanotechnol. Hur 10.1109/TNANO.2017.2663659 16 315 2017 Tunneling effects in a charge-plasma dopingless transistor 

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13. IEEE Electron Device Lett. Hur 10.1109/LED.2016.2540645 37 541 2016 Comprehensive analysis of gate-induced drain leakage in vertically stacked nanowire FETs: inversion-mode versus junctionless mode 

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14. IEEE Trans. Nanotechnol. Connelly 10.1109/TNANO.2003.820774 3 98 2004 A new route to zero-barrier metal source/drain MOSFETs 

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15. 2008 Silvaco Int., atlas user’s manual: device simulation software 

16. IEEE Trans. Electron Devices Lixin 10.1109/16.981219 49 287 2002 Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs 

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17. Hoffmann 725 2005 GIDL (gate-induced drain leakage) and parasitic Schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices 

18. IEEE Trans. Electron Devices Larson 10.1109/TED.2006.871842 53 1048 2006 Overview and status of metal S/D Schottky-barrier MOSFET technology 

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19. Saitoh 30 1999 35 nm metal gate SOI-p-MOSFETs with PtSi Schottky source/drain 

20. IEEE Trans. Electron Devices Sahay 10.1109/TED.2017.2702067 64 3007 2017 Spacer design guidelines for nanowire FETs from gate-induced drain leakage perspective 

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21. IEEE Trans. Electron Devices Boucart 10.1109/TED.2007.899389 54 1725 2007 Double-gate tunnel FET with high-κ gate dielectric 

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22. IEEE Trans. Electron Devices Gundapaneni 10.1109/TED.2012.2185800 59 1023 2012 Effect of band-to-band tunneling on junctionless transistors 

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23. IEEE Trans. Electron Devices Vega 10.1109/TED.2009.2026318 56 2016 2009 Dopant-segregated Schottky source/drain double-gate MOSFET design in the direct source-to-drain tunneling regime 

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