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NTIS 바로가기IEEE transactions on electron devices, v.68 no.8, 2021년, pp.4051 - 4056
Park, Yeong-Hun (Samsung Electronics, Foundry Division, Yongin, South Korea) , Yi, Boram (Korea University, Sejong, South Korea) , Kim, Seung-Hwan (SK Hynix, Research and Development Division, Icheon, South Korea) , Shim, Ju-Hyun (Korea University, Sejong, South Korea) , Song, Hyeong-Sub (Chungnam National University, Daejeon, South Korea) , Song, Hyun-Dong (Chungnam National University, Daejeon, South Korea) , Shin, Hyun-Jin (Chungnam National University, Daejeon, South Korea) , Lee, Hi-Deok (Chungnam National University, Daejeon, South Korea) , Yang, Ji-Woon (Korea University, Sejong, South Korea)
Analytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current–voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate diele...
Sajjad, Redwan N., Radhakrishna, Ujwal, Antoniadis, Dimitri A.. A tunnel FET compact model including non-idealities with verilog implementation. Solid-state electronics, vol.150, 16-22.
Lin, Yen-Kai, Khandelwal, Sourabh, Duarte, Juan Pablo, Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming. A Predictive Tunnel FET Compact Model With Atomistic Simulation Validation. IEEE transactions on electron devices, vol.64, no.2, 599-605.
Noor, Fatimah Arofiati, Bimo, Christoforus, Syuhada, Ibnu, Winata, Toto, Khairurrijal, Khairurrijal. A compact model for gate tunneling currents in undoped cylindrical surrounding-gate metal-oxide-semiconductor field-effect transistors. Microelectronic engineering, vol.216, 111086-.
Horst, Fabian, Farokhnejad, Atieh, Zhao, Qing-Tai, Iñíguez, Benjamín, Kloes, Alexander. 2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs. IEEE transactions on electron devices, vol.66, no.1, 132-138.
Neves, Felipe S., Agopian, Paula G. D., Martino, Joao Antonio, Cretu, Bogdan, Rooyackers, Rita, Vandooren, Anne, Simoen, Eddy, Voon-Yew Thean, Aaron, Claeys, Cor. Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source. IEEE transactions on electron devices, vol.63, no.4, 1658-1665.
Bu, S.T., Huang, D.M., Jiao, G.F., Yu, H.Y., Li, M.F.. Low frequency noise in tunneling field effect transistors. Solid-state electronics, vol.137, 95-101.
Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.. A physics-based MOSFET noise model for circuit simulators. IEEE transactions on electron devices, vol.37, no.5, 1323-1333.
Shin, Hyun-Jin, Song, Hyun-Dong, Song, Hyeong-Sub, Eadi, Sunil Babu, Choi, Hyun-Woong, Kim, Seong-Hyun, Kim, Do-Woo, Lee, Hi-Deok, Kwon, Hyuk-Min. Correlation between low-frequency noise and interface traps of fully-depleted silicon-on-insulator tunneling FETs induced by hot carrier stress. Japanese journal of applied physics, vol.59, no.10, 100903-.
Shen, C., Yang, L.T., Samudra, G., Yeo, Y.C.. A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET. Solid-state electronics, vol.57, no.1, 23-30.
Tripathy, Manas Ranjan, Singh, Ashish Kumar, Samad, A., Chander, Sweta, Baral, Kamalaksha, Singh, Prince Kumar, Jit, Satyabrata. Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications. IEEE transactions on electron devices, vol.67, no.3, 1285-1292.
Lyu, Zhijun, Lv, Hongliang, Zhang, Yuming, Zhang, Yimen, Zhu, Yi, Sun, Jiale, Li, Miao, Lu, Bin. A Novel High-Performance Planar InAs/GaSb Face-Tunneling FET With Implanted Drain for Leakage Current Reduction. IEEE transactions on electron devices, vol.68, no.3, 1313-1317.
Choi, Woo Young, Park, Byung-Gook, Lee, Jong Duk, Liu, Tsu-Jae King. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.28, no.8, 743-745.
Xu, Wanjie, Wong, Hei, Iwai, Hiroshi, Liu, Jun, Qin, Pei. Analytical modeling on the drain current characteristics of gate-all-around TFET with the incorporation of short-channel effects. Solid-state electronics, vol.138, 24-29.
Kim, Hyun Woo, Kwon, Daewoong. Steep Switching Characteristics of L-Shaped Tunnel FET With Doping Engineering. IEEE journal of the Electron Devices Society, vol.9, 359-364.
Kato, Kimihiko, Asai, Hidehiro, Fukuda, Koichi, Mori, Takahiro, Morita, Yukinori. Si bilayer tunnel field-effect transistor structure realized using tilted ion-implantation technique. Solid-state electronics, vol.180, 107993-.
Universal analytic model for tunnel FET circuit simulation. Solid-state electronics, vol.108, 110-117.
Seabaugh, Alan C., Zhang, Qin. Low-Voltage Tunnel Transistors for Beyond CMOS Logic. Proceedings of the IEEE, vol.98, no.12, 2095-2110.
BSIM 4 1 0 MOSFET Model Users Manual 2010
Sentaurus Device User Guide vol H-2013 03 2013
Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.. A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors. IEEE transactions on electron devices, vol.37, no.3, 654-665.
De Michielis, L., Lattanzio, L., Ionescu, A. M.. Understanding the Superlinear Onset of Tunnel-FET Output Characteristic. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.33, no.11, 1523-1525.
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