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NTIS 바로가기IEEE electron device letters : a publication of the IEEE Electron Devices Society, v.24 no.3, 2003년, pp.150 - 152
Sasaki, T. (Semicond. Leading Edge Technol. Inc., Ibaraki, Japan) , Kuwazawa, K. , Tanaka, K. , Kato, J. , Dim-Lee Kwong
During evaluation of negative bias temperature instability (NBTI) in short-channel devices, we found that using an optimized nitrogen depth profile is important in suppressing NBTI when scaling down CMOS devices. Performing the NO anneal process before oxidation yeilds good transistor performance, s...
Ogawa, Shigeo, Shimaya, Masakazu, Shiono, Noboru. Interface-trap generation at ultrathin SiO2 (4-6 nm)-Si interfaces during negative-bias temperature aging. Journal of applied physics, vol.77, no.3, 1137-1148.
Blat, C. E., Nicollian, E. H., Poindexter, E. H.. Mechanism of negative-bias-temperature instability. Journal of applied physics, vol.69, no.3, 1712-1720.
IEEE Trans on Electron Devices bias temperature instability in scaled p $+$ polysilicon gate p-mosfet's yamamoto 1999 10.1109/16.760398 46 921
Liu, Chuan-Hsi, Lee, Ming T., Lin, Chih-Yung, Chen, Jenkon, Loh, Y. T., Liou, Fu-Tai, Schruefer, Klaus, Katsetos, Anastasios A., Yang, Zhijian, Rovedo, Nivo, Hook, Terence B., Wann, Clement, Chen, Tze-Chiang. Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs. Japanese journal of applied physics. Part 1, Regular papers, short notes and review papers, vol.41, no.b4, 2423-2425.
Abadeer, W.W., Tonti, W.R., Hansch, W.E., Schwalke, U.. Long-term bias temperature reliability of P+ polysilicon gated FET devices. IEEE transactions on electron devices, vol.42, no.2, 360-362.
Proc Symp VLSI Technology nbti enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10- $\mu\hbox{m}$ gate cmos generation kimizuka 2000 92
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