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NTIS 바로가기IEEE journal of solid-state circuits, v.38 no.11, 2003년, pp.1943 - 1951
Cho, Uk-Rae (SRAM Memory Div., Samsung Electron., Gyeonggi-Do, South Korea) , Kim, Tae-Hyoung , Yoon, Yong-Jin , Lee, Jong-Cheol , Bae, Dae-Gi , Kim, Nam-Seog , Kim, Kang-Young , Son, Young-Jae , Yang, Jeong-Suk , Sohn, Kwon-Il , Kim, Sung-Tae , Lee, In-Yeol , Lee, Kwang-Jin , Kang, Tae-Gyoung , Kim, Su-Chul , Ahn, Kee-Sik , Byun, Hyun-Geun
A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0°, 90°, and 270° are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of ±4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-μm CMOS process with five metals. The cell size and the chip size are 0.845 μm2 and 151.1 mm2, respectively.
Symp VLSI Tech Dig Tech Papers sub- $\mu\hbox{m}^{2}$ high density embedded sram technologies for 100 nm generation soc and beyond tomita 2002 14
IEDM Tech Dig a 1.29 $\mu\hbox{m}^{2}$ full cmos ultra-low power sram cell with 0.12 $\mu\hbox{m}$ spacer-on-stopper (sos) cmos technology kim 2001 253
Gabara, T.J., Knauer, S.C.. Digitally adjustable resistors in CMOS for high-performance applications. IEEE journal of solid-state circuits, vol.27, no.8, 1176-1185.
Chappell, T.I., Chappell, B.A., Schuster, S.E., Allan, J.W., Klepner, S.P., Joshi, R.V., Franch, R.L.. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE journal of solid-state circuits, vol.26, no.11, 1577-1585.
Saeki, T., Nakaoka, Y., Fujita, M., Tanaka, A., Nagata, K., Sakakibara, K., Matano, T., Hoshino, Y., Miyano, K., Isa, S., Nakazawa, S., Kakehashi, E., Drynan, J.M., Komuro, M., Fukase, T., Iwasaki, H., Takenaka, M., Sekine, J., Igeta, M., Nakanishi, N., Itani, T., Yoshida, I., Yoshino, K., Hashimoto, S., Yoshii, T., Ichinose, M., Imura, T., Uziie, M., Kikuchi, S., Koyama, K., Fukuzo, Y., Okuda, T.. A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. IEEE journal of solid-state circuits, vol.31, no.11, 1656-1668.
IEDM Tech Dig a high density 0.10 $\mu\hbox{m}$ cmos technology using low k dielectric and copper interconnect parihar 2001 249
IEDM Tech Dig high performance 50 nm cmos devices for microprocessor and embedded processor core application huang 2001 237
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