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NTIS 바로가기IEEE transactions on electron devices, v.57 no.2, 2010년, pp.466 - 473
Tsuji, Y. (Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan) , Terai, M. (Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan) , Fujieda, S. (Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan) , Syo, T. (Microcomput. Oper. Unit, NEC Electron. Corp., Sagamihara, Japan) , Saito, T. (Microcomput. Oper. Unit, NEC Electron. Corp., Sagamihara, Japan) , Ando, K. (Microcomput. Oper. Unit, NEC Electron. Corp., Sagamihara, Japan)
We profiled the lateral charge distribution in a split-gate silicon-oxide-nitride-oxide-silicon (SONOS) memory device with a short gate length (~ 40 nm) after channel hot-electron (CHE) injection or band-to-band tunneling-induced hot-hole (BTBT-HH) injection. The profiles were drawn from measurement...
Kuo-Tung Chang, Wei-Ming Chen, Swift, C., Higman, J.M., Paulson, W.M., Ko-Min Chang. A new SONOS memory using source-side injection for programming. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.19, no.7, 253-255.
Lusky, E., Shacham-Diamand, Y., Mitenberg, G., Shappir, A., Bloom, I., Eitan, B.. Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices. IEEE transactions on electron devices, vol.51, no.3, 444-451.
Kumar, P.B., Nair, P.R., Sharma, R., Kamohara, S., Mahapatra, S.. Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection. IEEE transactions on electron devices, vol.53, no.4, 698-705.
IEDM Tech Dig physical modeling of retention in localized trapping nitride memory devices arnaud 2006 1
Groeseneken, G., Maes, H.E., Beltran, N., De Keersmaecker, R.F.. A reliable approach to charge-pumping measurements in MOS transistors. IEEE transactions on electron devices, vol.31, no.1, 42-53.
Eitan, B., Pavan, P., Bloom, I., Aloni, E., Frommer, A., Finzi, D.. NROM: A novel localized trapping, 2-bit nonvolatile memory cell. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.21, no.11, 543-545.
IEDM Tech Dig an embedded 90 nm sonos nonvolatile memory utilizing hot electron programming and uniform tunnel erase swift 2002 927
Terai, M., Tsuji, Y., Kotsuji, S., Fujieda, S., Ando, K.. Trapped-Hole-Enhanced Erase-Level Shift by FN-Stress Disturb in Sub-90-nm-Node Embedded SONOS Memory. IEEE transactions on electron devices, vol.55, no.6, 1464-1471.
Minami, S.-i., Kamigaki, Y.. A novel MONOS nonvolatile memory device ensuring 10-year data retention after 107 erase/write cycles. IEEE transactions on electron devices, vol.40, no.11, 2011-2017.
Janai, M., Eitan, B., Shappir, A., Lusky, E., Bloom, I., Cohen, G.. Data retention reliability model of NROM nonvolatile memory products. IEEE transactions on device and materials reliability : a publication of the IEEE Electron Devices Society and the IEEE Reliability Society, vol.4, no.3, 404-415.
Proc IRPS new degradation mode of program disturb immunity of sub 90-nm node split-gate sonos memory tsuji 2008 699
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