[논문]A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

Hyung-Joon Chi; Young-Ho Choi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park; Jong-Jin Lim; Pil-Sung Kang; Bu-Yeol Lee; Jin-Cheol Hong; Hee-Sub Lee

doi:10.1109/TCSII.2011.2164158

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, v.58 no.10, 2011년, pp.687 - 691

Hyung-Joon Chi (Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Young-Ho Choi (Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Soo-Min Lee (Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Jae-Yoon Sim (Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Hong-June Park (Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Jong-Jin Lim (R&D Center, LG Display Co., Ltd., Paju, South Korea) , Pil-Sung Kang (R&D Center, LG Display Co., Ltd., Paju, South Korea) , Bu-Yeol Lee (R&D Center, LG Display Co., Ltd., Paju, South Korea) , Jin-Cheol Hong (R&D Center, LG Display Co., Ltd., Paju, South Korea) , Hee-Sub Lee (R&D Center, LG Display Co., Ltd., Paju, South Korea)

Abstract ▼ AI-Helper

A 2-Gb/s point-to-point intrapanel interface for thin-film-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input (`1111100000'). At the RX, a multiphase DLL follows the deskew DLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e-12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 mm2 and 52.4 mW at 2 Gbps with a 0.18- μm complementary metal-oxide-semiconductor process and a 1.8-V supply.

참고문헌 (11)

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원문보기 상세보기
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A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

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A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

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