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NTIS 바로가기Nanotechnology, v.22 no.31, 2011년, pp.315201 -
Park, Jea-Gun (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) , Kim, Seong-Je (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) , Shin, Mi-Hee (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) , Song, Seung-Hyun (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) , Chung, Sung-Woong (Hynix Semiconductor Incorporated, Amiri, Bubaleup, Icheonsi, Gyeonggido 467-701, Republic of Korea) , Enomoto, Hirofumi (Sumco Corporation, 4-3146-12 Hachimanpara, Yonezawa-shi, Yamagata 992-1128, Japan) , Shim, Tae-Hun (National Pr)
A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal–oxide–semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enha...
Ohsawa, T., Fujita, K., Higashi, T., Iwata, Y., Kajiyama, T., Asao, Y., Sunouchi, K.. Memory design using a one-transistor gain cell on SOI. IEEE journal of solid-state circuits, vol.37, no.11, 1510-1522.
1989 23 Proc. IEDM Tech. Dig. Sunouchi K
2009 Process Integration, Device, and Structure
2004 69 Proc. IEDM Tech. Dig. Kim D H
Moon, Hui-Chang, Kim, Seong-Je, Shim, Tae-Hun, Park, Jea-Gun. Impact of the top silicon thickness on phonon-limited electron mobility in (110)-oriented ultrathin-body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors. Journal of applied physics, vol.102, no.6, 063520-.
Lee, Yong-Seon, Shim, Tae-Hun, Yoo, Sang-Dong, Park, Jea-Gun. Silicon thickness fluctuation scattering dependence of electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors. Journal of applied physics, vol.103, no.8, 084503-.
2001 153 Proc. IEEE Int. SOI Conf. Okhonin S Nagoga M Sallese J M Fazan P
Hamamoto, Takeshi, Minami, Yoshihiro, Shino, Tomoaki, Kusunoki, Naoki, Nakajima, Hiroomi, Morikado, Mutsuo, Yamada, Takashi, Inoh, Kazumi, Sakamoto, Atsushi, Higashi, Tomoki, Fujita, Katsuyuki, Hatsuda, Kosuke, Ohsawa, Takashi, Nitayama, Akihiro. A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability. IEEE transactions on electron devices, vol.54, no.3, 563-571.
Choi, Ki-Ryoung, Lee, Choong-Hyun, Kim, Seong-Je, Enomoto, Hirofumi, Shim, Tae-Hun, Cho, Won-Ju, Park, Jea-Gun. Dependence of memory margin of Cap-less memory cells on top Si thickness. Applied physics letters, vol.94, no.2, 023508-.
Kim, Seong-Je, Oh, Jung-Mi, Shim, Tae-Hun, Park, Jea-Gun. Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator. Japanese journal of applied physics, vol.49, no.r3, 036507-.
Kim, Seong-Je, Kim, Tae-Hyun, Shim, Tae-Hun, Park, Jea-Gun. Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator. Applied physics letters, vol.96, no.16, 163508-.
2009 10.1088/0268-1242/24/3/035014 24 035014 0268-1242 Semicond. Sci. Technol. Kim S J
Gomez, L., Aberg, I., Hoyt, J.L.. Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.28, no.4, 285-287.
26 ICSICT 2006, 8th Int. Conf. Yoshimi M Cayrefourcq I Mazure C
Bruel, M.. Silicon on insulator material technology. Electronics letters, vol.31, no.14, 1201-1202.
Seong-Je, Tae-Hun, Jea-Gun, Myung-Ho, Won-Ju. Post-RTA Effect on the Electrical Characteristics ofNano-Scale Strained Si Grown on SiGe-on-Insulator n-MOSFET. Journal of the Korean Physical Society, vol.50, no.2, 514-.
Shim, Tae-Hun, Kim, Seong-Je, Park, Jea-Gun. (Semiconductors) Dependence of Electrical Characteristics on Si Thickness and Ge Concentration for Unstrained Si Grown on Strained SiGe-on-Insulator n-Metal?Oxide?Semiconductor Field-Effect Transistor. Japanese journal of applied physics. Part 1, Regular papers, short notes and review papers, vol.46, no.6, 3324-3329.
Price, P.J. Two-dimensional electron transport in semiconductor layers. I. Phonon scattering. Annals of physics, vol.133, no.2, 217-239.
Takagi, S., Toriumi, A., Iwase, M., Tango, H.. On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation. IEEE transactions on electron devices, vol.41, no.12, 2363-2368.
Gámiz, F., Cartujo-Cassinello, P., Roldán, J. B., Jiménez-Molinos, F.. Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates. Journal of applied physics, vol.92, no.1, 288-295.
1972 10 Semiconductors and Semimetals Rode D L
2004 281 Proc. IEDM Tech. Dig. Shino T
2005 307 Proc. IEDM Tech. Dig. Minami Y
2007 168 Symp. VLSI Tech. Dig. Oh C W
Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Hon-Sum Philip Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, vol.89, no.3, 259-288.
1994 895 Ext. Abst. SSDM Koga J Takagi S Toriumi A
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