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A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

Nanotechnology, v.22 no.31, 2011년, pp.315201 -   

Park, Jea-Gun (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) ,  Kim, Seong-Je (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) ,  Shin, Mi-Hee (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) ,  Song, Seung-Hyun (National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea) ,  Chung, Sung-Woong (Hynix Semiconductor Incorporated, Amiri, Bubaleup, Icheonsi, Gyeonggido 467-701, Republic of Korea) ,  Enomoto, Hirofumi (Sumco Corporation, 4-3146-12 Hachimanpara, Yonezawa-shi, Yamagata 992-1128, Japan) ,  Shim, Tae-Hun (National Pr)

Abstract AI-Helper 아이콘AI-Helper

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal–oxide–semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enha...

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