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NTIS 바로가기IEEE journal of solid-state circuits, v.47 no.1, 2012년, pp.75 - 84
Fukuda, K. (Toshiba Corp., Yokohama, Japan) , Watanabe, Y. (Toshiba Corp., Yokohama, Japan) , Makino, E. (Toshiba Corp., Yokohama, Japan) , Kawakami, K. (Toshiba Corp., Yokohama, Japan) , Sato, J. (Toshiba Corp., Yokohama, Japan) , Takagiwa, T. (Toshiba Corp., Yokohama, Japan) , Kanagawa, N. (Toshiba Corp., Yokohama, Japan) , Shiga, H. (Toshiba Corp., Yokohama, Japan) , Tokiwa, N. (Toshiba Corp., Yokohama, Japan) , Shindo, Y. (Toshiba Corp., Yokohama, Japan) , Ogawa, T. (Toshiba Corp., Yokohama, Japan) , Edahiro, T. (Toshiba Corp., Yokohama, Japan) , Iwai, M. (Toshiba Corp., Yokohama, Japan) , Nagao, O. (Toshiba Corp., Yokohama, Japan) , Musha, J. (Toshiba Corp., Yokohama, Japan) , Minamoto, T. (Toshiba Corp., Yokohama, Japan) , Furuta, Y. (Toshiba Corp., Yokohama, Japan) , Yanagidaira, K. (Toshiba Corp., Yokohama, Japan) , Suzuki, Y. (Toshiba Corp., Yokohama, Japan) , Nakamura, D. (Toshiba Corp., Yokohama, Japan) , Hosomura, Y. (Toshiba Corp., Yokohama, Japan) , Tanaka, R. (Toshiba Corp., Yokohama, Japan) , Komai, H. (Toshiba Corp., Yokohama, Japan) , Muramoto, M. (Toshiba Corp., Yokohama, Japan) , Shikata, G. (Toshiba Corp., Yokohama, Japan) , Yuminaka, A. (Toshiba Corp., Yokohama, Japan) , Sakurai, K. (Toshiba Memory Syst. Corp., Yokohama, Japan) , Sakai, M. (SanDisk Corp., Yokohama, Japan) , Hong Ding (Toshiba Corp., Yokohama, Japan) , Watanabe, M. (Toshiba Corp., Yokohama, Japan) , Kato, Y. , Miwa, T. , Mak, A. , Nakamichi, M. , Hemink, G. , Lee, D. , Higashitani, M. , Murphy, B. , Bo Lei , Matsunaga, Y. , Naruke, K. , Hara, T.
A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optim...
IEEE ISSCC Dig Tech Papers A 151 ${\hbox{mm}}^{2}$ 64 Gb MLC NAND flash memory in 24 nm CMOS technology fukuda 2011 198
Takeuchi, Ken, Kameda, Yasushi, Fujimura, Susumu, Otake, Hiroyuki, Hosono, Koji, Shiga, Hitoshi, Watanabe, Yoshihisa, Futatsuyama, Takuya, Shindo, Yoshihiko, Kojima, Masatsugu, Iwai, Makoto, Shirakawa, Masanobu, Ichige, Masayuki, Hatakeyama, Kazuo, Tanaka, Shinichi, Kamei, Teruhiko, Fu, Jia-Yi, Cernea, Adi, Li, Yan, Higashitani, Masaaki, Hemink, Gertjan, Sato, Shinji, Oowada, Ken, Lee, Shih-Chung, Hayashida, Naoki, Wan, Jun, Lutze, Jeffrey, Tsao, Shouchang, Mofidi, Mehrdad, Sakurai, Kiyofumi, Tokiwa, Naoya, Waki, Hiroko, Nozawa, Yasumitsu, Kanazawa, Kazuhisa, Ohshima, Shigeo.
A 56-nm CMOS 99-
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IEEE ISSCC Dig Tech Papers A 159 ${\hbox{mm}}^{2}$ 32 nm MLC NAND-flash memory with 200 MB/s asynchronous DDR interface hyunggon 2010 442
IEEE ISSCC Dig Tech Papers A 34 MB/s-program-throughput 16 Gb MLC NAND with all-bitline architecture in 56 nm cernea 2008 420
IEEE ISSCC Dig Tech Papers A 120 ${\hbox{mm}}^{2}$ 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology kanda 2008 430
Tanaka, T., Tanaka, Y., Nakamura, H., Sakui, K., Oodaira, H., Shirota, R., Ohuchi, K., Masuoka, F., Hara, H.. A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE journal of solid-state circuits, vol.29, no.11, 1366-1373.
Hara, T., Fukuda, K., Kanazawa, K., Shibata, N., Hosono, K., Maejima, H., Nakagawa, M., Abe, T., Kojima, M., Fujiu, M., Takeuchi, Y., Amemiya, K., Morooka, M., Kamei, T., Nasu, H., Wang, Chi-Ming, Sakurai, K., Tokiwa, N., Waki, H., Maruyama, T., Yoshikawa, S., Higashitani, M., Pham, T.D., Fong, Yupin, Watanabe, T.. A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. IEEE journal of solid-state circuits, vol.41, no.1, 161-169.
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