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IEEE journal of the Electron Devices Society, v.5 no.3, 2017년, pp.164 - 169
Huang, Ya-Chi (Department of Electrical Engineering, Institute of Microelectronics, National Cheng Kung University, Tainan, Taiwan) , Chiang, Meng-Hsueh (Department of Electrical Engineering, Institute of Microelectronics, National Cheng Kung University, Tainan, Taiwan) , Wang, Shui-Jinn , Fossum, Jerry G.
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Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integrat...
10.1109/IEDM.2016.7838516
10.1109/IEDM.2016.7838515
Veloso, Anabela, Cho, Moon Ju, Simoen, Eddy, Hellings, Geert, Matagne, Philippe, Collaert, Nadine, Thean, Aaron. (Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics. ECS transactions, vol.72, no.2, 85-95.
Trivedi, V.P., Fossum, J.G., Chowdhury, M.M.. Nanoscale FinFETs With Gate-Source/Drain Underlap. IEEE transactions on electron devices, vol.52, no.1, 56-62.
Liang-Teck Pang, Kun Qian, Spanos, C.J., Nikolic, B.. Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology. IEEE journal of solid-state circuits, vol.44, no.8, 2233-2243.
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Trivedi, V.P., Fossum, J.G.. Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.26, no.8, 579-582.
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IEDM Tech Dig A 14nm logic technology featuring $2^{\mathrm{ nd}}$ -generation FinFET, air-gapped interconnects, self-aligned double patterning and a $0.0588~\mu $ m2 SRAM cell size natarajan 2014 3.7.1
Trong Huynh-Bao, Sakhare, Sushil, Yakimets, Dmitry, Ryckaert, Julien, Thean, Aaron Voon-Yew, Mercha, Abdelkarim, Verkest, Diederik, Wambacq, Piet. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs. IEEE transactions on electron devices, vol.63, no.2, 643-651.
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10.1109/IEDM.2016.7838441
10.1109/IEDM.2016.7838456
Fossum, Jerry G., Zhou, Zhenming, Mathew, Leo, Nguyen, Bich-Yen. SOI versus bulk-silicon nanoscale FinFETs. Solid-state electronics, vol.54, no.2, 86-89.
10.1017/CBO9781139343466
Chenyun Pan, Raghavan, Praveen, Yakimets, Dmitry, Debacker, Peter, Catthoor, Francky, Collaert, Nadine, Tokei, Zsolt, Verkest, Diederik, Thean, Aaron Voon-Yew, Naeemi, Azad. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node. IEEE transactions on electron devices, vol.62, no.10, 3125-3132.
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