[논문]A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

Abdulrazzaq, Bilal I.; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.

doi:10.1186/s40064-016-2090-z

[해외논문] A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance 원문보기

SpringerPlus, v.5 no.1, 2016년, pp.434 -

Abdulrazzaq, Bilal I. (Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia) , Abdul Halin, Izhal (Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia) , Kawahito, Shoji (Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011 Japan) , Sidek, Roslina M. (Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia) , Shafie, Suhaidi (Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia) , Yunus, Nurul Amziah Md. (Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia)

Abstract ▼ AI-Helper

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

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