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NTIS 바로가기Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on, 2015 Mar, 2015년, pp.1 - 6
Srivatsava, G. S. R. (Dept. of Electr. Eng., Indian Inst. of Technol., Indore, Indore, India) , Singh, Pooran (Dept. of Electr. Eng., Indian Inst. of Technol., Indore, Indore, India) , Gaggar, Siddharth (Dept. of Electr. Eng., Indian Inst. of Technol., Indore, Indore, India) , Vishvakarma, Santosh Kumar (Dept. of Electr. Eng., Indian Inst. of Technol., Indore, Indore, India)
Clock gating is an effective technique for minimizing dynamic power in sequential circuits. This paper aims at reducing the power of a dual port register memory by removing the unwanted switching activity on a major portion of the clock network using clock gating. To realize this, two register based...
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