Kim, Hyungmin
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Lee, Daniel Juhun
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Park, Soyoun
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Nho, Taemin
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Shin, YoungChul
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Kim, Seongkweon
(Seoul National University of Science and Technology, Seoul, South Korea)
,
Shim, Dong Ha
(Seoul National University of Science and Technology, Seoul, South Korea)
Recently, neuromorphic research has been drawing attentions as there is a limitation of a serial processor with a Von Neumann architecture. In particular, spiking neural network (SNN) is one of the neuromorphic AI models that has been actively researched because it can be implemented with a low powe...
Recently, neuromorphic research has been drawing attentions as there is a limitation of a serial processor with a Von Neumann architecture. In particular, spiking neural network (SNN) is one of the neuromorphic AI models that has been actively researched because it can be implemented with a low power consumption and a parallel signal processing system. Non-volatile semiconductors are currently used for SNN implementation, but they still have limitations due to problems with production cost and compatibility with silicon devices. Therefore, in this paper, a new SNN model using CMOS is proposed and proved through post simulation with cadence MMSIM. For the current mode neuromorphic implementation, the pattern recognition of the full current mode SNN system was confirmed by modeling the system with MATLAB SIMULINK
Recently, neuromorphic research has been drawing attentions as there is a limitation of a serial processor with a Von Neumann architecture. In particular, spiking neural network (SNN) is one of the neuromorphic AI models that has been actively researched because it can be implemented with a low power consumption and a parallel signal processing system. Non-volatile semiconductors are currently used for SNN implementation, but they still have limitations due to problems with production cost and compatibility with silicon devices. Therefore, in this paper, a new SNN model using CMOS is proposed and proved through post simulation with cadence MMSIM. For the current mode neuromorphic implementation, the pattern recognition of the full current mode SNN system was confirmed by modeling the system with MATLAB SIMULINK
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