[해외논문]
Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
Electron Devices Meeting (IEDM), 2020 IEEE International,
2020 Dec 12,
2020년, pp.28.2.1 - 28.2.4
Belmonte, A.
(imec, Leuven, Belgium)
,
Oh, H.
(imec, Leuven, Belgium)
,
Rassoul, N.
(imec, Leuven, Belgium)
,
Donadio, G.L.
(imec, Leuven, Belgium)
,
Mitard, J.
(imec, Leuven, Belgium)
,
Dekkers, H.
(imec, Leuven, Belgium)
,
Delhougne, R.
(imec, Leuven, Belgium)
,
Subhechha, S.
(imec, Leuven, Belgium)
,
Chasin, A.
(imec, Leuven, Belgium)
,
van Setten, M. J.
(imec, Leuven, Belgium)
,
Kljucar, L.
(imec, Leuven, Belgium)
,
Mao, M.
(imec, Leuven, Belgium)
,
Puliyalil, H.
(imec, Leuven, Belgium)
,
Pak, M.
(imec, Leuven, Belgium)
,
Teugels, L.
(imec, Leuven, Belgium)
,
Tsvetanova, D.
(imec, Leuven, Belgium)
,
Banerjee, K.
(imec, Leuven, Belgium)
,
Souriau, L.
(imec, Leuven, Belgium)
,
Tokei, Z.
(imec, Leuven, Belgium)
,
Goux, L.
(imec, Leuven, Belgium)
,
Kar, G. S.
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layo...
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal Vth reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal Vth reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).
※ AI-Helper는 부적절한 답변을 할 수 있습니다.