Interruptible and re-entrant cache clean range instruction
원문보기
IPC분류정보
국가/구분 |
United States(US) Patent
공개
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국제특허분류(IPC7판) |
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출원번호 |
US-0157576
(2002-05-29)
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공개번호 |
US-0097550
(2003-05-22)
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우선권정보 |
EP-0402956 (2001-11-15) |
발명자
/ 주소 |
- Chauvel, Gerard
- Lasserre, Serge
- D'Inverno, Dominique
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대리인 / 주소 |
TEXAS INSTRUMENTS INCORPORATED
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인용정보 |
피인용 횟수 :
0 인용 특허 :
0 |
초록
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A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance wit
A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.
대표청구항
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1. A method for operating a digital system, comprising the steps of:a. executing a sequence of instructions in accordance with a program counter; b. receiving an interrupt request; c. suspending execution of the sequence of instructions by halting execution of a currently executing instruction befor
1. A method for operating a digital system, comprising the steps of:a. executing a sequence of instructions in accordance with a program counter; b. receiving an interrupt request; c. suspending execution of the sequence of instructions by halting execution of a currently executing instruction before it is completed if the currently executing instruction is an interruptible instruction; d. servicing the interrupt; and e. resuming execution of the interruptible instruction after returning from servicing the interrupt. 2. The method according to claim 1, wherein step “a” comprises the step of setting a first indicator bit to indicate that the currently executing instruction is an interruptible instruction. 3. The method according to claim 2, wherein step “c” comprises the steps of:saving a return program counter value that will cause the currently executing instruction to be re-executed if the currently executing instruction is an interruptible instruction; and saving a return program counter value that will not cause the currently executing instruction to be re-executed if the currently executing instruction is not an interruptible instruction. 4. The method according to claim 1, wherein step “c” further comprises the step of setting a second indicator bit to indicate that the currently executing instruction is being interrupted. 5. The method according claim 1, wherein step “e” comprises the steps of:comparing an initial parameter provided by the interruptible instruction with a current content of a control register used during execution of the interruptible instruction; if the same, resuming execution of the interruptible instruction using the current content of the control register, if different, restarting execution of the interruptible instruction by storing the initial parameter provided by interruptible instruction in the control register. 6. The method according to claim 5, wherein step “c” further comprises the step of setting a second indicator bit to indicate that the currently executing instruction is being interrupted; andwherein the step of comparing is conditioned on the second indicator bit indicating the interruptible instruction had been interrupted. 7. The method according to claim 1, wherein step “d” comprises executing another sequence of instructions that contain the interruptible instruction, such that a second copy of the interruptible instruction is executed while execution of a first copy of the interruptible instruction is suspended. 8. The method according to claim 7, wherein step “c” comprises performing a context switch by saving state information exclusive of modified parameters used during execution of the interruptible instruction. 9. The method according to claim 1, wherein the interruptible instruction cleans a range of addresses in a storage region specified by a start parameter and an end parameter, and wherein step “e” comprises the steps of:comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction; if the same, resuming execution of the clean instruction using the current content of the start register and end register, if different, restarting execution of the clean instruction by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. 10. The method according to claim 3, wherein step “c” comprises performing a context switch by saving state information exclusive of modified parameters used during execution of the interruptible instruction. 11. The method according claim 10, wherein step “e” comprises the steps of:comparing an initial parameter provided by the interruptible instruction with a current content of a control register used during execution of the interruptible instruction; if the same, resuming execution of the interruptible instruction using the current content of the control register, if different, restarting execution of the interruptible instruction by storing the initial parameter provided by interruptible instruction in the control register. 12. The method according to claim 11, wherein step “c” further comprises the step of setting a second indicator bit to ind icate that the currently executing instruction is being interrupted. 13. The method according to claim 12, wherein the step of comparing is conditioned on the second indicator bit indicating the interruptible instruction had been interrupted. 14. The method according to claim 13, wherein step “d” comprises executing another sequence of instructions that contain the interruptible instruction, such that a second copy of the interruptible instruction is executed while execution of a first copy of the interruptible instruction is suspended. 15. A digital system comprising:one or more interconnected processors connected to a cache memory and thereby to a backup memory; and wherein at least one of the one or more processors is operated according to the method of claim 1. 16. A digital system comprising:one or more interconnected processors connected to a cache memory and thereby to a backup memory; and wherein at least one of the one or more processors comprises:means for executing a sequence of instructions in accordance with a program counter; means for receiving an interrupt request; means for suspending execution of the sequence of instructions by halting execution of a currently executing instruction before it is completed if the currently executing instruction is an interruptible instruction; means for servicing the interrupt; and means for resuming execution of the interruptible instruction after returning from servicing the interrupt. 17. The digital system according to claim 16, further comprising means for saving a return program counter value that will cause the currently executing instruction to be re-executed if the currently executing instruction is an interruptible instruction or that will not cause the currently executing instruction to be re-executed if the currently executing instruction is not an interruptible instruction 18. The digital system according to claim 17 being a personal digital assistant, further comprising:a display, connected to the interconnected processors via a display adapter; radio frequency (RF) circuitry connected to interconnected processors; and an aerial connected to the RF circuitry.
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