A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than
A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.
대표청구항▼
1. A duty cycle correction circuit comprising: an averaging circuit configured to receive a first signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50%
1. A duty cycle correction circuit comprising: an averaging circuit configured to receive a first signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal; and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal. 2. The duty cycle correction circuit of claim 1, wherein the duty cycle of the fifth signal is 50%. 3. The duty cycle correction circuit of claim 1, wherein the first signal comprises a clock signal. 4. The duty cycle correction circuit of claim 1, wherein the fourth signal comprises an inverted clock signal. 5. The duty cycle correction circuit of claim 1, wherein the first signal has a first edge and the second signal has a second edge and the averaging circuit is configured to provide a third edge of the third signal between the first edge and the second edge. 6. The duty cycle correction circuit of claim 5, wherein the third edge is halfway between the first edge and the second edge. 7. The duty cycle correction circuit of claim 5, wherein the first edge is a rising edge, the second edge is a rising edge, and the third edge is a rising edge. 8. The duty cycle correction circuit of claim 1, wherein the third signal has a first edge and the fourth signal has a second edge and the duty restoration circuit is configured to provide the fifth signal having a logic high time equal to a time between the first edge and the second edge. 9. The duty cycle correction circuit of claim 8, wherein the first edge is a rising edge and the second edge is a rising edge. 10. The duty cycle correction circuit of claim 1, wherein the fifth signal has a falling edge and the synchronous mirror delay circuit is configured to receive a delayed fifth signal having a rising edge and provide the second signal having a rising edge at a time after the falling edge of the fifth signal equal to a time between the rising edge of the delayed fifth signal and the falling edge of the fifth signal. 11. A duty cycle correction system comprising: a first circuit configured to receive a clock signal and output a corrected clock signal having a first duty cycle closer to 50% than the clock signal; a second circuit configured to receive an inverted clock signal and output a corrected inverted clock signal having a second duty cycle closer to 50% than the inverted clock signal; and a third circuit configured to receive the corrected clock signal and the corrected inverted clock signal and provide a first signal having a third duty cycle closer to 50% than the corrected clock signal and the corrected inverted clock signal. 12. The duty cycle correction system of claim 11, wherein the first circuit comprises: an averaging circuit configured to receive the clock signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and the inverted clock signal and provide the corrected clock signal; and a synchronous mirror delay circuit configured to receive the corrected clock signal and provide the second signal. 13. The duty cycle correction system of claim 11, wherein the second circuit comprises: an averaging circuit configured to receive the inverted clock signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and the clock signal and provide the corrected inverted clock signal; and a synchronous mirror delay circuit configured to receive the corrected inverted clock signal and provide the second signal. 14. The duty cycle correction system of claim 11, wherein the third circuit is configured to provide the first signal having a first transition on a transition of the corrected clock signal and a second transition on a transition of the corrected inverted clock signal. 15. The duty cycle correction system of claim 14, wherein the first transition is a rising edge, the second transition is a falling edge, the transition of the corrected clock signal is a rising edge, and the transition of the corrected inverted clock signal is a rising edge. 16. The duty cycle correction system of claim 11, wherein the first circuit comprises: a first averaging circuit configured to receive the clock signal and a second signal and provide a third signal; a first duty restoration circuit configured to receive the third signal and the inverted clock signal and provide a fourth signal; a first synchronous mirror delay circuit configured to receive the fourth signal and provide the second signal; a second averaging circuit configured to receive the clock signal and a fifth signal and provide a sixth signal; a second duty restoration circuit configured to receive the sixth signal and the inverted clock signal and provide a seventh signal; a second synchronous mirror delay circuit configured to receive the seventh signal and provide the fifth signal; and a third averaging circuit configured to receive the fourth signal and the seventh signal and provide the corrected clock signal, wherein the second averaging circuit, the second duty restoration circuit, and the second synchronous mirror delay circuit are enabled one clock cycle after the first averaging circuit, the first duty cycle correction circuit, and the first synchronous mirror delay circuit. 17. The duty cycle correction system of claim 11, wherein the second circuit comprises: a first averaging circuit configured to receive the inverted clock signal and a second signal and provide a third signal; a first duty restoration circuit configured to receive the third signal and the clock signal and provide a fourth signal; a first synchronous mirror delay circuit configured to receive the fourth signal and provide the second signal; a second averaging circuit configured to receive the inverted clock signal and a fifth signal and provide a sixth signal; a second duty restoration circuit configured to receive the sixth signal and the clock signal and provide a seventh signal; a second synchronous mirror delay circuit configured to receive the seventh signal and provide the fifth signal; and a third averaging circuit configured to receive the fourth signal and the seventh signal and provide the corrected inverted clock signal, wherein the second averaging circuit, the second duty restoration circuit, and the second synchronous mirror delay circuit are enabled one clock cycle after the first averaging circuit, the first duty cycle correction circuit, and the first synchronous mirror delay circuit. 18. The duty cycle correction system of claim 11, further comprising: a fourth circuit configured to receive the corrected clock signal and output a second corrected clock signal having a fourth duty cycle closer to 50% than the corrected clock signal; a fifth circuit configured to receive the corrected inverted clock signal and output a second corrected inverted clock signal having a fifth duty cycle closer to 50% than the corrected inverted clock signal; and a sixth circuit configured to receive the second corrected clock signal and the second corrected inverted clock signal and output a second signal having a sixth duty cycle closer to 50% than the second corrected clock signal and the second corrected inverted clock signal. 19. The duty cycle correction system of claim 11, wherein the duty cycle of the first signal is 50% 20. A method for correcting the duty cycle of a clock signal, the method comprising: averaging a clock signal and a second signal to provide a third signal; generating a corrected clock signal having a duty cycle closer to 50% than the clock signal based on the third signal and an inverted clock signal; and synchronous mirror delaying the corrected clock signal to provide the second signal. 21. The method of claim 20, wherein generating the corrected clock signal comprises generating the corrected clock signal having a duty cycle of 50%. 22. The method of claim 20, wherein the clock signal has a first edge and the second signal has a second edge and averaging the clock signal and the second signal comprises providing a third edge of the third signal between the first edge and the second edge. 23. The method of claim 20, wherein the third signal has a first edge and the fourth signal has a second edge and generating the corrected clock signal comprises providing the corrected clock signal having a logic high time equal to a time between the first edge and the second edge. 24. The method of claim 20, wherein the corrected clock signal has a falling edge and synchronous mirror delaying the corrected clock signal comprises receiving a delayed corrected clock signal having a rising edge and providing the second signal having a rising edge at a time after the falling edge of the corrected clock signal equal to a time between the rising edge of the delayed corrected clock signal and the falling edge of the corrected clock signal. 25. A memory system comprising: a duty cycle correction circuit comprising: an averaging circuit configured to receive a first signal and a second signal and provide a third signal; a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal; and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal; and a memory circuit configured to receive the fifth signal and one of store and retrieve data. 26. The memory system of claim 25, wherein the duty cycle correction circuit and the memory circuit are a single semiconductor chip. 27. The memory system of claim 25, wherein the memory circuit comprises a dynamic random access memory. 28. The memory system of claim 25, wherein the memory circuit comprises a synchronous dynamic random access memory. 29. The memory system of claim 25, wherein the memory circuit comprises a double data rate synchronous dynamic random access memory.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.