초록 ▼

Signal value storage circuitry 2 is provided which includes a first transistor stack, a second transistor stack and a third transistor stack. The signal value storage circuitry is controlled by a single clock signal. Keeper transistors and isolation transistors serve to permit static operation of th

Signal value storage circuitry 2 is provided which includes a first transistor stack, a second transistor stack and a third transistor stack. The signal value storage circuitry is controlled by a single clock signal. Keeper transistors and isolation transistors serve to permit static operation of the signal value storage circuitry (i.e. the clock signal may be stopped without losing state) and to prevent contention within the circuitry.

대표청구항 ▼

1. Signal value storage circuitry comprising: a signal input configured to receive an input signal value;a signal output configured to output an output signal value;a clock signal input configured to receive a single clock signal varying between a first clock signal level and a second clock signal l

1. Signal value storage circuitry comprising: a signal input configured to receive an input signal value;a signal output configured to output an output signal value;a clock signal input configured to receive a single clock signal varying between a first clock signal level and a second clock signal level;a first transistor stack, coupled to said signal input and to said clock signal input, is configured to drive a primary node bearing a primary node signal to a primary node signal level dependent upon said input signal value while said single clock signal has said first clock signal level;a second transistor stack, coupled to said primary node and to said clock signal input, is configured to charge a secondary node bearing a secondary node signal to a charged signal level while said single clock signal has said first clock signal level and, while said single clock signal has said second clock signal level, one of (i) to discharge said secondary node to a discharged signal level if said primary node signal has a first signal level, and (ii) not to discharge said secondary node if said primary node signal has a second signal level;a third transistor stack, coupled to said secondary node, to said clock signal input and to said signal output, is configured to drive said output signal value while said clock signal has said second clock signal level to one of: (i) a first output signal level if said secondary node is at said charged signal level, and (ii) a second output signal level if said secondary node is at said discharged signal level; anda secondary-node keeper transistor, coupled to said primary node and to said secondary node, is configured (i) to drive said secondary node to maintain said charged signal level when said primary node signal has said second signal level and (ii) not to drive said secondary node when said primary node signal has said first signal level. 2. Signal value storage circuitry as claimed in claim 1, comprising: a first primary-node keeper transistor, coupled to said primary node and to said secondary node, is configured (i) to drive said primary node to maintain said first signal level when said secondary node is at said discharged signal level and (ii) to not drive said primary node when said secondary node signal is at said charged signal level. 3. Signal value storage circuitry as claimed in claim 1, comprising: a second primary-node keeper transistor, coupled to said primary node and to said second transistor stack, is configured (i) while said single clock signal has said second clock signal level, to drive said primary node to maintain said second signal level when said primary node is at said second signal level and (ii) while said single clock signal has said first clock signal level, to not drive said primary node. 4. Signal value storage circuitry as claimed in claim 1, wherein said first transistor stack includes a first-stack isolation transistor, coupled to said secondary node, configured to prevent said first transistor stack driving said primary node to said second signal level when said secondary node is at said discharged signal level. 5. Signal value storage circuitry as claimed in claim 1, wherein said third transistor stack includes a third-stack isolation transistor, coupled to said primary node, configured to prevent said third transistor stack driving said signal output toward said first output signal level while said secondary node is discharged from said charged signal level to said discharged signal level. 6. Signal value storage circuitry as claimed in claim 1, comprising: output feedback circuitry, coupled to said signal output, configured to maintain said output signal at a current level while said single clock signal has said first clock signal level and to permit said output signal to change while said single clock signal has said second clock signal level. 7. Signal value storage circuitry comprising: signal input means for receiving an input signal value;signal output means for outputting an output signal value;clock signal input means for receiving a single clock signal varying between a first clock signal level and a second clock signal level;first transistor stack means, coupled to said signal input means and to said clock signal input means, for driving primary node means for bearing a primary node signal to a primary node signal level dependent upon said input signal value while said single clock signal has said first clock signal level;second transistor stack means, coupled to said primary node means and to said clock signal input means, for charging secondary node means for bearing a secondary node signal to a charged signal level while said single clock signal has said first clock signal level and, while said single clock signal has said second clock signal level, one of (i) discharging said secondary node means to a discharged signal level if said primary node signal has a first signal level, and (ii) not discharging said secondary node means if said primary node signal has a second signal level;third transistor stack means, coupled to said secondary node means, to said clock signal input means and to said signal output means, for driving said output signal value while said clock signal has said second clock signal level to one of: (i) a first output signal level if said secondary node means is at said charged signal level, and (ii) a second output signal level if said secondary node means is at said discharged signal level; andsecondary-node keeper transistor means, coupled to said primary node means and to said secondary node means, for (i) driving said secondary node means to maintain said charged signal level when said primary node signal has said second signal level and (ii) not driving said secondary node means when said primary node signal has said first signal level. 8. A method of storing a signal value within signal value storage circuitry, said method comprising the steps of: receiving an input signal value at a signal input;receiving at a clock signal input a single clock signal varying between a first clock signal level and a second clock signal level;driving, with a first transistor stack coupled to said signal input and to said clock signal input, a primary node bearing a primary node signal to a primary node signal level dependent upon said input signal value while said single clock signal has said first clock signal level;charging, with a second transistor stack coupled to said primary node and to said clock signal input, a secondary node bearing a secondary node signal to a charged signal level while said single clock signal has said first clock signal level and, while said single clock signal has said second clock signal level, one of (i) discharging said secondary node to a discharged signal level if said primary node signal has a first signal level, and (ii) not discharging said secondary node if said primary node signal has a second signal level;driving, with a third transistor stack coupled to said secondary node, to said clock signal input and to a signal output, an output signal value while said clock signal has said second clock signal level to one of: (i) a first output signal level if said secondary node is at said charged signal level, and (ii) a second output signal level if said secondary node is at said discharged signal level;outputting said output signal value at said signal output; andwith a secondary-node keeper transistor coupled to said primary node and to said secondary node (i) driving said secondary node to maintain said charged signal level when said primary node signal has said second signal level and (ii) not driving said secondary node when said primary node signal has said first signal level. 9. A method as claimed in claim 8, comprising: with a first primary-node keeper transistor coupled to said primary node and to said secondary node, (i) driving said primary node to maintain said first signal level when said secondary node is at said discharged signal level and (ii) not driving said primary node when said secondary node signal is at said charged signal level. 10. A method as claimed in claim 8, comprising: with a second primary-node keeper transistor coupled to said primary node and to said second transistor stack, (i) while said single clock signal has said second clock signal level, driving said primary node to maintain said second signal level when said primary node is at said second signal level and (ii) while said single clock signal has said first clock signal level, not driving said primary node. 11. A method as claimed in claim 8, comprising: with a first-stack isolation transistor within said first transistor stack and coupled to said secondary node, preventing said first transistor stack driving said primary node to said second signal level when said secondary node is at said discharged signal level. 12. A method as claimed in claim 8, comprising: with a third-stack isolation transistor within said third transistor stack and coupled to said primary node, preventing said third transistor stack driving said signal output toward said first output signal level while said secondary node is discharged from said charged signal level to said discharged signal level. 13. A method as claimed in claim 8, comprising: with output feedback circuitry coupled to said signal output, maintaining said output signal at a current level while said single clock signal has said first clock signal level and permitting said output signal to change while said single clock signal has said second clock signal level.