[미국특허]
Display Backplane and Method of Fabricating the Same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
G09G-003/32
H01L-027/12
H01L-029/786
H01L-027/32
출원번호
US-0231586
(2014-03-31)
공개번호
US-0243220
(2015-08-27)
발명자
/ 주소
Kim, Hyoung-Su
Cho, Namwook
Kim, TaeHwan
Lee, Jaemyon
출원인 / 주소
LG Display Co., Ltd.
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide se
There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).
대표청구항▼
1. A display comprising: a thin-film-transistor (TFT) backplane having an oxide TFT and an low-temperature-poly-silicon (LTPS) TFT on a same substrate. 2. The display of claim 1, wherein the TFT backplane includes at least one active area and at least one non-display area, wherein said at least one
1. A display comprising: a thin-film-transistor (TFT) backplane having an oxide TFT and an low-temperature-poly-silicon (LTPS) TFT on a same substrate. 2. The display of claim 1, wherein the TFT backplane includes at least one active area and at least one non-display area, wherein said at least one display area includes a plurality of pixel circuits implemented with oxide TFTs and said at least one non-display area includes at least one driving circuit implemented with LTPS TFTs. 3. The display of claim 2, wherein said at least one driving circuit implemented with LTPS TFTs in the non-display area of the TFT backplane is a gate driver for supplying one or more gate signals to the pixel circuits. 4. The display of claim 1, wherein the TFT backplane includes a plurality of pixel circuits and at least one driving circuit implemented on the same substrate, wherein at least one of the plurality of pixel circuits include at least one oxide TFT and at least one LTPS TFT. 5. The display of claim 3, wherein said at least one of the plurality of pixel circuits include at least one oxide TFT and at least one LTPS TFT, which are connected in parallel to each other. 6. The display of claim 4, wherein gates of said at least one oxide TFT and at least one LTPS TFT connected in parallel to each other are connected to a same data line. 7. The display of claim 1, wherein the TFT backplane includes a plurality of pixel circuits comprises: a first switching TFT having a terminal connected to a first node, the first node being connected to a storage capacitor and a gate of a driving TFT;a second switching TFT having a terminal connected to a second node, the second node being connected to a first terminal of the driving TFT and an organic light emitting diode (OLED); anda third switching TFT having a first terminal connected to a high level voltage line and a second terminal connected to a second terminal of the driving TFT, wherein the third switching TFT has a poly-silicon semiconductor active layer 8. The display of claim 7, wherein the third switching TFT is a P-Type TFT having a poly-silicon semiconductor active layer, which is configured to supply a high level voltage from the high level voltage line to the second terminal of the driving TFT when a high level gate signal is applied to a gate of the third switching TFT. 9. The display of claim 7, wherein the first switching TFT and the second switching TFT have an oxide semiconductor active layer, and wherein the driving TFT has the poly-silicon semiconductor active layer. 10. The display of claim 7, wherein the storage capacitor includes a first capacitor and a second capacitor that are serially connected to each other. 11. The display of claim 10, wherein the first storage capacitor is formed between the gate of the driving TFT and a source of the driving TFT, and wherein the second storage capacitor is formed between the source of the driving TFT and the second terminal of the third switching TFT. 12. The display of claim 10, wherein the first storage capacitor is formed between the gate of the driving TFT and the first terminal of the driving TFT, and wherein the second storage capacitor is formed between the first terminal of the driving TFT and an initial voltage line supplying an initialization voltage. 13. The display of claim 10, wherein the first storage capacitor is formed between the gate of the driving TFT and the first terminal of the driving TFT, and wherein the second storage capacitor is formed between the first terminal of the driving TFT and a low level voltage line supplying an low level voltage. 14. The display of claim 1, wherein the TFT backplane includes a plurality of pixel circuits and at least one driving circuit implemented on the same substrate, wherein at least one of the driving circuits include at least one oxide TFT and at least one LTPS TFT. 15. The display of claim 14, wherein the driving circuit that includes at least one oxide TFT and at least one LTPS TFT is a gate driver for supplying a plurality of gate signals to the plurality of pixel circuits. 16. The display of claim 14, wherein the driving circuit that includes at least one oxide TFT and at least one LTPS TFT is an invert circuit coupled to a gate driver for inverting at least one gate signal to the plurality of pixel circuits. 17. The display of claim 14, wherein the driving circuit that includes at least one oxide TFT and at least one LTPS TFT is a switching circuit coupled to a gate driver for controlling output of at least one gate signal to the plurality of pixel circuits. 18. A method of driving a display, comprising: turning on a first switching thin-film-transistor (TFT) and a second switching TFT in a plurality of pixel circuits to initialize a first node and a second node;turning on the first switching TFT and a third switching TFT to sense a threshold voltage of a driving TFT in the plurality of pixel circuits;turning on the first switching TFT to write a data voltage into a storage capacitor in the plurality of pixel circuits; andturning on the third switching element to cause the driving TFT to supply drive current to an organic light emitting diodes in the plurality of pixel circuits. 19. The method of claim 18, further comprising: preventing a gate driver from supplying at least one gate signal on a gate line connected to the plurality of pixel circuits for a predetermined frames. 20. A display device, comprising: a plurality of pixel circuits formed in an active area of a substrate; andat least one driving circuit formed in a non-display area of the substrate, wherein the plurality of pixel circuits include at least one switching TFT connected to a storage capacitor with an oxide semiconductor active layer, and wherein said at least one driving circuit include a switching circuit for causing a gate driver from supplying a gate signal to some of the pixel circuits.
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