MULTI-LAYER WORK FUNCTION METAL GATES WITH SIMILAR GATE THICKNESS TO ACHIEVE MULTI-VT FOR VFETS
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IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01L-021/8234
H01L-027/092
H01L-021/8238
H01L-027/088
H01L-029/49
H01L-029/66
출원번호
US-0788469
(2017-10-19)
공개번호
US-0294191
(2018-10-11)
발명자
/ 주소
Bao, Ruqiang
Jagannathan, Hemanth
Jamison, Paul C.
Lee, ChoongHyun
출원인 / 주소
Bao, Ruqiang
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four
A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.
대표청구항▼
1. A structure for forming a device having multiple field effect transistors (FETs) with each FET having a different work function, the structure comprising: first, second, third, and fourth FETs formed over a semiconductor substrate;an interfacial layer and a high-k dielectric layer formed over the
1. A structure for forming a device having multiple field effect transistors (FETs) with each FET having a different work function, the structure comprising: first, second, third, and fourth FETs formed over a semiconductor substrate;an interfacial layer and a high-k dielectric layer formed over the first, second, third, and fourth FETs;a first work function conducting layer formed over the high-k dielectric layer, where the first work function conducting layer is subsequently removed from the third FET;a second work function conducting layer, where the first and second work function conducting layers are subsequently removed from the second FET;a third work function conducting layer, where the first, second, and third work function conducting layers are subsequently removed from the first FET;a fourth work function conducting layer;a sacrificial block layer and a sacrificial cap layer, the sacrificial block layer and the sacrificial cap layer subsequently removed from the first and second FETs;a fifth work function conducting layer and a patterning cap layer, where the patterning cap layer, the fifth work function conducting layer, the sacrificial cap, and the sacrificial block layer are subsequently removed from the third and fourth FETs; andfirst and second conducting layers formed over the first, second, third, and fourth FETs. 2. The structure of claim 1, wherein an organic planarization layer (OPL) is deposited and subsequently recessed. 3. The structure of claim 2, wherein the remaining work function conducting layers from the first, second, third, and fourth FETs are recessed to expose a hard mask of each of the first, second, third, and fourth FETs. 4. The structure of claim 3, wherein the OPL is stripped. 5. The structure of claim 4, wherein a dielectric layer is deposited up to a top surface of the hard mask of each of the first, second, third, and fourth FETs. 6. The structure of claim 5, wherein the dielectric layer is recessed and spacers are formed. 7. The structure of claim 6, wherein isolation patterning of the first, second, third, and fourth FETs is performed. 8. The structure of claim 7, wherein an insulator is deposited between the recesses formed by the isolation patterning. 9. The structure of claim 8, wherein a top portion of a channel of each of the first, second, third, and fourth FETs is exposed by etching. 10. The structure of claim 9, wherein source and/or drain regions and contacts are formed over the channel of each of the first, second, third, and fourth FETs. 11. A structure for forming a device having a plurality of field effect transistors (FETs) with each FET having a different work function, the structure comprising: at least one dielectric layer formed over the plurality of FETs;a first work function conducting layer formed over the at least one dielectric layer, where the first work function conducting layer is subsequently removed from a first FET;a second work function conducting layer, where the first and second work function conducting layers are subsequently removed from a second FET;a third work function conducting layer, where the first, second, and third work function conducting layers are subsequently removed from a third FET;a fourth work function conducting layer;at least one sacrificial layer, where the at least one sacrificial layer is subsequently removed from the second and third FETs;a fifth work function conducting layer, where the fifth work function conducting layer and the at least one sacrificial layer are subsequently removed from at least the first FET; andat least one conducting layer formed over the plurality of FETs;wherein multi-layer work function metal gates of each of the plurality of FETs have a similar gate thickness. 12. The structure of claim 11, wherein an organic planarization layer (OPL) is deposited and subsequently recessed. 13. The structure of claim 12, wherein the remaining work function conducting layers from the plurality of FETs are recessed to expose a hard mask of each of the plurality of FETs. 14. The structure of claim 13, wherein the OPL is stripped. 15. The structure of claim 14, wherein a dielectric layer is deposited up to a top surface of the hard mask of each of the plurality of FETs. 16. The structure of claim 15, wherein the dielectric layer is recessed and spacers are formed. 17. The structure of claim 16, wherein isolation patterning of the plurality of FETs is performed. 18. The structure of claim 17, wherein an insulator is deposited between the recesses formed by the isolation patterning. 19. The structure of claim 18, wherein a top portion of a channel of each of the plurality of FETs is exposed by etching. 20. The structure of claim 19, wherein source and/or drain regions and contacts are formed over the channel of each of the plurality of FETs.
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