[미국특허]
HYBRID COMPENSATION CIRCUIT AND METHOD FOR OLED PIXEL
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IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
G09G-003/3258
G09G-003/3233
G09G-003/3266
G09G-003/3275
출원번호
15505097
(2016-12-20)
공개번호
20190156747
(2019-05-23)
우선권정보
CN-201610899709.9 (2016-10-14)
국제출원번호
PCT/CN2016/110903
(2016-12-20)
발명자
/ 주소
Nie, Chenglei
Wu, Yuanchun
출원인 / 주소
Nie, Chenglei
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
The invention discloses a hybrid compensation circuit and method for OLED pixel, by using a pixel internal driver circuit (100) of 4T1C structure to compensate threshold voltage of driving TFT using the source follow approach to achieve fast compensation; and in driving light-emitting phase, using a
The invention discloses a hybrid compensation circuit and method for OLED pixel, by using a pixel internal driver circuit (100) of 4T1C structure to compensate threshold voltage of driving TFT using the source follow approach to achieve fast compensation; and in driving light-emitting phase, using an external compensation circuit (200) to detect the current flowing through the OLED (D1), comparing, computing and storing the difference between the current flowing through the OLED (D1) and a pre-defined current; when the corresponding row of pixel internal driver circuits (100) entering the threshold voltage programming design phase again, performing compensation on the data signal (Data), correcting compensation result so that the current flowing through the OLED (D1) is closer to the pre-defined current to achieve large compensation range.
대표청구항▼
1. A hybrid compensation circuit for OLED pixel, which comprises: a plurality of pixel internal driver circuits arranged in an array, and an external compensation circuit electrically connected respectively to each row of the plurality of pixel internal driver circuits; each pixel internal driver ci
1. A hybrid compensation circuit for OLED pixel, which comprises: a plurality of pixel internal driver circuits arranged in an array, and an external compensation circuit electrically connected respectively to each row of the plurality of pixel internal driver circuits; each pixel internal driver circuit comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a first capacitor, and an organic light-emitting diode (OLED);the first TFT having the gate connected to a first node, the source connected to a second node and the drain connected to a voltage power supply;the second TFT having the gate connected to a first scan signal, the source connected to a data signal and the drain connected to the first node;the third TFT having the gate connected to a second scan signal, the source connected to an initialization voltage and the drain connected to the first node;the fourth TFT having the gate connected to the second scan signal, the source connected to the initialization voltage and the drain connected to the second node;the first capacitor having one end connected to the first node and the other end connected to the second node;the OLED having the anode connected to the second node and the cathode connected to the ground;each external compensation circuit comprising: an analog-to-digital converter (ADC), a current comparator, a control module, a memory, and a digital-to-analog converter (DAC);the ADC having the input end connected to the drain of the first TFT of corresponding row of pixel internal driver circuits, and the output end connected to the input end of the current comparator;the current comparator having the output end connected to the input end of the control module;the control module having the output end connected to the input end of the memory;the memory having the output end connected to the input end of the DAC; andthe DAC having the output end connected to the source of the second TFT of corresponding row of pixel internal driver circuits. 2. The hybrid compensation circuit for OLED pixel as claimed in claim 1, wherein the external compensation circuit further comprises an operational amplifier and a second capacitor; the operational amplifier having the first input end connected to the drain of the first TFT of the pixel internal driver circuit, the second input end connected to the ground, and the output end connected to the input end of the ADC;the second capacitor having one end connected to the first input end of the operational amplifier and the other end connected to the output end of the operational amplifier. 3. The hybrid compensation circuit for OLED pixel as claimed in claim 1, wherein the first TFT, the second TFT, the third TFT and the fourth TFT are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs or amorphous silicon (a-Si) TFTs; the first scan signal and the second scan signal are both provided by an external timing controller. 4. The hybrid compensation circuit for OLED pixel as claimed in claim 1, wherein the first scan signal, the second scan signal and the data signal are combined to correspond, in series, to a reset phase, a threshold voltage detection phase, a threshold voltage programming design phase and a driving light-emitting phase; in the reset phase, the first scan signal provides low voltage, the second scan signal provides high voltage and the data signal provides low voltage;in the threshold voltage detection phase, the first scan signal provides high voltage, the second scan signal provides low voltage and the data signal provides a reference high voltage;in the threshold voltage programming design phase, the first scan signal provides high voltage, the second scan signal provides low voltage and the data signal provides a display data signal high voltage;in the driving light-emitting phase, the first scan signal, the second scan signal and the data signal all provide low voltage. 5. The hybrid compensation circuit for OLED pixel as claimed in claim 4, wherein the reference high voltage is lower than the display data signal high voltage. 6. A hybrid compensation method for OLED pixel, which comprises: Step 1: providing a hybrid compensation circuit for OLED pixel,which comprising: a plurality of pixel internal driver circuits arranged in an array, and an external compensation circuit electrically connected respectively to each row of the plurality of pixel internal driver circuits;each pixel internal driver circuit comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a first capacitor, and an organic light-emitting diode (OLED);the first TFT having the gate connected to a first node, the source connected to a second node and the drain connected to a voltage power supply;the second TFT having the gate connected to a first scan signal, the source connected to a data signal and the drain connected to the first node;the third TFT having the gate connected to a second scan signal, the source connected to an initialization voltage and the drain connected to the first node;the fourth TFT having the gate connected to the second scan signal, the source connected to the initialization voltage and the drain connected to the second node;the first capacitor having one end connected to the first node and the other end connected to the second node;the OLED having the anode connected to the second node and the cathode connected to the ground;each external compensation circuit comprising: an analog-to-digital converter (ADC), a current comparator, a control module, a memory, and a digital-to-analog converter (DAC);the ADC having the input end connected to the drain of the first TFT of corresponding row of pixel internal driver circuits, and the output end connected to the input end of the current comparator;the current comparator having the output end connected to the input end of the control module;the control module having the output end connected to the input end of the memory;the memory having the output end connected to the input end of the DAC; and the DAC having the output end connected to the source of the second TFT of corresponding row of pixel internal driver circuits;Step 2: entering reset phase:the first scan signal providing low voltage to cut off the second TFT, the second scan signal providing high voltage to turn on the third TFT and the fourth TFT, the initialization voltage being written into the first node (i.e., the gate of the first TFT) and the second node (i.e., the source of the first TFT), and the data signal providing low voltage;Step 3: entering threshold voltage detection phase:the first scan signal providing high voltage to turn on the second TFT, the second scan signal providing low voltage to cut off the third TFT and the fourth TFT, the data signal providing a reference high voltage Vref, the first node (i.e., the gate of the first TFT) being written into with the reference high voltage and the second node (i.e., the source of the first TFT) becoming Vref−Vth, with Vth being the threshold voltage of the first TFT;Step 4: entering threshold voltage programming design phase:the first scan signal providing high voltage to turn on the second TFT, the second scan signal providing low voltage to cut off the third TFT and the fourth TFT, the data signal providing a display data signal high voltage, the first node (i.e., the gate of the first TFT) being written into with the display data signal high voltage and the second node (i.e., the source of the first TFT) becoming Vref−Vth+ΔV, with ΔV being influence on the second node caused by the display data signal high voltage;Step 5: entering driving light-emitting phase:the first scan signal, the second scan signal and the data signal all providing low voltage, the second TFT, the third TFT and the fourth TFT all cut off, the voltage difference between the first node and the second node remaining unchanged due to storage effect of the first capacitor; the OLED emitting light and current flowing through the OLED independent of the threshold voltage of the first TFT;the ADC also receiving and converting the current flowing through the OLED by the corresponding row of pixel internal driver circuits to obtain an actual current detection signal, the current comparator comparing the actual current detection signal with a pre-defined current corresponding signal, the control module computing the difference between the actual current detection signal and the pre-defined current corresponding signal and storing the difference in the memory;Step 6: when the corresponding row of pixel internal driver circuits entering the threshold voltage programming design phase again, the memory outputting the stored difference to the DAC for conversion and performing compensation on the data signal. 7. The hybrid compensation method for OLED pixel as claimed in claim 6, wherein the external compensation circuit further comprises an operational amplifier and a second capacitor; the operational amplifier has the first input end connected to the drain of the first TFT of the pixel internal driver circuit, the second input end connected to the ground, and the output end connected to the input end of the ADC;the second capacitor having one end connected to the first input end of the operational amplifier and the other end connected to the output end of the operational amplifier;in Step 5, the current flowing the OLED by the corresponding row of pixel internal driver circuits is amplified by the operational amplifier and outputted to the input end of the ADC. 8. The hybrid compensation method for OLED pixel d as claimed in claim 6, wherein the first TFT, the second TFT and the third TFT are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs or amorphous silicon (a-Si) TFTs; the first scan signal and the second scan signal are both provided by an external timing controller. 9. The hybrid compensation method for OLED pixel as claimed in claim 6, wherein the reference high voltage is lower than the display data signal high voltage. 10. A hybrid compensation circuit for OLED pixel, which comprises: a plurality of pixel internal driver circuits arranged in an array, and an external compensation circuit electrically connected respectively to each row of the plurality of pixel internal driver circuits; each pixel internal driver circuit comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a first capacitor, and an organic light-emitting diode (OLED);the first TFT having the gate connected to a first node, the source connected to a second node and the drain connected to a voltage power supply;the second TFT having the gate connected to a first scan signal, the source connected to a data signal and the drain connected to the first node;the third TFT having the gate connected to a second scan signal, the source connected to an initialization voltage and the drain connected to the first node;the fourth TFT having the gate connected to the second scan signal, the source connected to the initialization voltage and the drain connected to the second node;the first capacitor having one end connected to the first node and the other end connected to the second node;the OLED having the anode connected to the second node and the cathode connected to the ground;each external compensation circuit comprising: an analog-to-digital converter (ADC), a current comparator, a control module, a memory, and a digital-to-analog converter (DAC);the ADC having the input end connected to the drain of the first TFT of corresponding row of pixel internal driver circuits, and the output end connected to the input end of the current comparator;the current comparator having the output end connected to the input end of the control module;the control module having the output end connected to the input end of the memory;the memory having the output end connected to the input end of the DAC; andthe DAC having the output end connected to the source of the second TFT of corresponding row of pixel internal driver circuits;the external compensation circuit further comprising an operational amplifier and a second capacitor;the operational amplifier having the first input end connected to the drain of the first TFT of the pixel internal driver circuit, the second input end connected to the ground, and the output end connected to the input end of the ADC;the second capacitor having one end connected to the first input end of the operational amplifier and the other end connected to the output end of the operational amplifier;wherein the first TFT, the second TFT, the third TFT and the fourth TFT are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs or amorphous silicon (a-Si) TFTs;the first scan signal and the second scan signal are both provided by an external timing controller. 11. The hybrid compensation circuit for OLED pixel as claimed in claim 10, wherein the first scan signal, the second scan signal and the data signal are combined to correspond, in series, to a reset phase, a threshold voltage detection phase, a threshold voltage programming design phase and a driving light-emitting phase; in the reset phase, the first scan signal provides low voltage, the second scan signal provides high voltage and the data signal provides low voltage;in the threshold voltage detection phase, the first scan signal provides high voltage, the second scan signal provides low voltage and the data signal provides a reference high voltage;in the threshold voltage programming design phase, the first scan signal provides high voltage, the second scan signal provides low voltage and the data signal provides a display data signal high voltage;in the driving light-emitting phase, the first scan signal, the second scan signal and the data signal all provide low voltage. 12. The hybrid compensation circuit for OLED pixel as claimed in claim 10, wherein the reference high voltage is lower than the display data signal high voltage.
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