A Lidar system includes a focal-plane array having a plurality of pixels. Each pixel includes a first single-photon avalanche diode (SPAD) and a second SPAD. The Lidar system operates by, for each of a plurality of the pixels, applying a bias voltage to the first SPAD of the pixel while no bias volt
A Lidar system includes a focal-plane array having a plurality of pixels. Each pixel includes a first single-photon avalanche diode (SPAD) and a second SPAD. The Lidar system operates by, for each of a plurality of the pixels, applying a bias voltage to the first SPAD of the pixel while no bias voltage or low bias voltage is applied to the second SPAD of the pixel, then removing the bias voltage from the first SPAD of the pixel and applying a bias voltage to the second SPAD of the pixel while no bias voltage or low bias voltage is applied to the first SPAD of the pixel, and then recording detection of a photon by the first SPAD of the pixel and detection of a photon by the second SPAD on a common memory bank of the pixel.
대표청구항▼
1. A method comprising: emitting light from a light emitter;applying a bias voltage to a first single-photon avalanche diode (SPAD) of a pixel;detecting a photon with the first SPAD;removing the bias voltage from the first SPAD after detecting the photon with the first SPAD;applying a bias voltage t
1. A method comprising: emitting light from a light emitter;applying a bias voltage to a first single-photon avalanche diode (SPAD) of a pixel;detecting a photon with the first SPAD;removing the bias voltage from the first SPAD after detecting the photon with the first SPAD;applying a bias voltage to a second SPAD of the pixel after detecting the photon with the first SPAD and while no bias voltage or low bias voltage is applied to the first SPAD;quenching the first SPAD during application of bias voltage to second SPAD. 2. The method as set forth in claim 1, further comprising recording the detection of the photon by the first SPAD in a memory bank of the pixel. 3. The method as set forth in claim 2, further comprising detecting a photon with the second SPAD and recording the detection of the photon by the second SPAD in the memory bank of the pixel. 4. The method as set forth in claim 3, further comprising: removing the bias voltage from the second SPAD after detecting the photon with the second SPAD;applying a bias voltage to the first SPAD after detecting the photon with the second SPAD and while no bias voltage or low bias voltage is applied to the second SPAD; andquenching the second SPAD after detection of the photon with the second SPAD and during application of the bias voltage to the first SPAD. 5. The method as set forth in claim 2, wherein recording the detection of the photon by the first SPAD in the memory bank is during the application of bias voltage to the second SPAD. 6. The method as set forth in claim 1, further comprising: removing the bias voltage from the second SPAD after detecting the photon with the second SPAD;applying a bias voltage to the first SPAD after detecting the photon with the second SPAD and while no bias voltage or low bias voltage is applied to the second SPAD; andquenching the second SPAD after detection of the photon with the second SPAD and during application of the bias voltage to the first SPAD. 7. The method as set forth in claim 1, further comprising: applying a bias voltage to a third SPAD of the pixel simultaneously with the application of the bias voltage to the first SPAD;removing the bias voltage from the third SPAD after detecting the photon with the first SPAD. 8. The method as set forth in claim 7, further comprising: removing the bias voltage from the second SPAD after detecting the photon with the second SPAD;simultaneously applying a bias voltage to the first SPAD and the third SPAD after detecting the photon with the second SPAD and while no bias voltage or low bias voltage is applied to the second SPAD; andquenching the second SPAD after detection of the photon with the second SPAD and during application of the bias voltage to the first SPAD and the third SPAD. 9. The method as set forth in claim 7, further comprising: applying a bias voltage to a fourth SPAD of the pixel simultaneously with the application of the bias voltage to the second SPAD;removing the bias voltage from the second SPAD and the fourth SPAD after detecting the photon with the second SPAD. 10. The method as set forth in claim 9, further comprising: simultaneously applying a bias voltage to the first SPAD and the third SPAD after detecting the photon with the second SPAD and while no bias voltage or low bias voltage is applied to the second SPAD and the third SPAD; andquenching the second SPAD after detection of the photon with the second SPAD and during application of the bias voltage to the first SPAD and the third SPAD. 11. The method as set forth in claim 1, wherein removing the bias voltage from the first SPAD after detecting the photon with the first SPAD and applying the bias voltage to a second SPAD of the pixel after detecting the photon with the first SPAD is in response to the detection of the photon by the first SPAD. 12. The method as set forth in claim 1, wherein the application of the bias voltage to the first SPAD is clocked based on the emission of light from the light emitter. 13. The method as set forth in claim 1, wherein removing the bias voltage from the first SPAD and applying the bias voltage to the second SPAD is a periodic timing pattern. 14. A Lidar system comprising: a focal-plane array having a plurality of pixels, each pixel including a first single-photon avalanche diode (SPAD) and a second SPAD; anda computer having a processor and a memory storing instructions executable by the processor to: for each of a plurality of the pixels, apply a bias voltage to the first SPAD while no bias voltage or low bias voltage is applied to the second SPAD;remove the bias voltage from the first SPAD of the pixel and apply a bias voltage to the second SPAD of the pixel while no bias voltage or low bias voltage is applied to the first SPAD of the pixel; andrecord detection of a photon by the first SPAD of the pixel and detection of a photon by the second SPAD of the pixel on a common memory bank of the pixel. 15. The Lidar system as set forth in claim 14, wherein the memory stores instructions to repeatedly alternate the bias voltage between the first SPAD and the second SPAD in response to detection of a photon by the one of the first SPAD and the second SPAD that receives bias voltage. 16. The Lidar system as set forth in claim 15, wherein the memory stores instructions to quench the first SPAD during application of bias voltage to the second SPAD and to quench the second SPAD during application of bias voltage to the first SPAD. 17. The Lidar system as set forth in claim 14, wherein the memory stores instructions to remove the bias voltage from the first SPAD and apply the bias voltage to the second SPAD while no bias voltage or low bias voltage is applied to the first SPAD in response to the detection of a photon by the first SPAD. 18. The Lidar system as set forth in claim 17, wherein the memory stores instructions to remove the bias voltage from the second SPAD and apply a bias voltage to the first SPAD while no bias voltage or low bias voltage is applied to the second SPAD in response to the detection of a photon by the second SPAD. 19. The Lidar system as set forth in claim 14, wherein the memory stores instructions to alternate the bias voltage between the first SPAD and the second SPAD in a periodic timing pattern. 20. The Lidar system as set forth in claim 14, wherein the memory stores instructions to quench the first SPAD during application of bias voltage to the second SPAD. 21. The Lidar system as set forth in claim 14, wherein the memory stores instructions to: apply a bias voltage to a third SPAD of the pixel simultaneously with the application of the bias voltage to the first SPAD; andremove the bias voltage from the third SPAD simultaneously with the removal of the bias voltage from the first SPAD. 22. The Lidar system as set forth in claim 21, wherein the memory stores instructions to: apply a bias voltage to a fourth SPAD of the pixel simultaneously with the application of the bias voltage to the second SPAD;remove the bias voltage from the fourth SPAD simultaneously with the removal of the bias voltage from the second SPAD. 23. A computer having a processor and a memory storing instructions executable by the processor to: emit light from a light emitter;apply a bias voltage to a first single-photon avalanche diode (SPAD) of a pixel while no bias voltage or low bias voltage is applied to a second SPAD of the pixel;remove the bias voltage from the first SPAD and apply a bias voltage to the second SPAD of the pixel while no bias voltage or low bias voltage is applied to the first SPAD; andrecord detection of a photon by the first SPAD and detection of a photon by the second SPAD on a common memory bank of the pixel. 24. The computer as set forth in claim 23, wherein the memory stores instructions to repeatedly alternate the bias voltage between the first SPAD and the second SPAD in response to detection of a photon by the one of the first SPAD and the second SPAD that receives bias voltage. 25. The computer as set forth in claim 24, wherein the memory stores instructions to quench the first SPAD during application of bias voltage to the second SPAD and to quench the second SPAD during application of bias voltage to the first SPAD. 26. The computer as set forth in claim 23, wherein the memory stores instructions to remove the bias voltage from the first SPAD and apply the bias voltage to the second SPAD while no bias voltage or low bias voltage is applied to the first SPAD in response to the detection of a photon by the first SPAD. 27. The computer as set forth in claim 26, wherein the memory stores instructions to remove the bias voltage from the second SPAD and apply a bias voltage to the first SPAD while no bias voltage or low bias voltage is applied to the second SPAD in response to the detection of a photon by the second SPAD. 28. The computer as set forth in claim 23, wherein the memory stores instructions to alternate the bias voltage between the first SPAD and the second SPAD in a periodic timing pattern. 29. The computer as set forth in claim 23, wherein the memory stores instructions to quench the first SPAD during application of bias voltage to the second SPAD. 30. The computer as set forth in claim 23, wherein the memory stores instructions to: apply a bias voltage to a third SPAD of the pixel simultaneously with the application of the bias voltage to the first SPAD; andremove the bias voltage from the third SPAD simultaneously with the removal of the bias voltage from the first SPAD. 31. The computer as set forth in claim 30, wherein the memory stores instructions to: apply a bias voltage to a fourth SPAD of the pixel simultaneously with the application of the bias voltage to the second SPAD;remove the bias voltage from the fourth SPAD simultaneously with the removal of the bias voltage from the second SPAD.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.