[특허]Computer memory addressing employing base and index registers

Computer memory addressing employing base and index registers 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/00
출원번호	US-0531016 (1974-12-09)
발명자 / 주소	Crabb Robert P. (San Diego CA) Unger Robert A. (El Cajon CA) Gilbreath Jim A. (San Diego CA)
출원인 / 주소	The United States of America as represented by the Secretary of the Navy (Washington DC 06)
인용정보	피인용 횟수 : 32 인용 특허 : 0

초록 ▼

A memory addressing system which enables a computer to address a total of 1,048,575 words (32 times its original capacity) with minimal impact upon existing software. The method employed by this invention involves a new dual usage of the b (index) designator in each instruction word so that in addition to its normal function of specifying which of 8 index registers is to be added to the address portion of the instruction, it also specifies which of 8 base registers is to be arithmetically added to the basic 15-bit address to determine the final 20-bit absolute memory location address. A total of 262,144 words may be accessed by this dual use of the b designator for any one setting of the base registers. Each program module is designed to operate in a 32,768 word environment and no coding changes need be made to it; the computer operator need only maintain the appropriate offset values in the base registers for the module currently in operation.

대표청구항 ▼

A system for computer memory addressing which permits accessing to an original, internal, memory of a computer whose capacity in words is no longer adequate as well as to an additional, external, memory which extends the capacity to an adequate level, the system comprising: means for accessing an instruction word generated by the internal memory, the word including an M-bit index designator and an N-bit operand address designator; an index register, each of whose cells have the capability of containing N bits; a base register, each of whose cells have the capability of containing N +K bits, for offsetting all addresses in a given class by a given amount; means connected to the accessing means to receive the index designator for simultaneously accessing corresponding cells in the index and base registers; a first adder, coupled to receive the operand address designator and the accessed signal of the index register; a second adder, coupled to receive the output signal of the first adder and the accessed signal of the base register; and; a comparator, whose input is the output of the second adder, which compares the magnitude of the address of the instruction word with the magnitude of a word generated within the comparator representing the capacity of the original internal memory, and generates an output signal which is alternatively directed to 1. the internal memory if the magnitude of the address of the instruction word is at least equal to the capacity of the internal memory; and 2. to the external memory if the magnitude of the address of the instruction word is greater than the capacity of the internal memory.

이 특허를 인용한 특허 (32)

Ahuja Sudhir R. (Matawan NJ), Accessing arrangement for interleaved modular memories.
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Ikuta Hiroaki (Yokohama JA) Naruke Yoshikazu (Kawasaki JA) Nagasawa Yoshio (Tokyo JA) Yakushi Masanori (Kawasaki JA), Address extending control unit.
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Butwell Justin R. (Milton NY) Scalzi Casper A. (Poughkeepsie NY) Schmalz Richard J. (Wappingers Falls NY), Address generating mechanism for multiple virtual spaces.
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Kaufman, Marc, Address translator.
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Matsumoto Keiji (Tokyo JPX), Addressing system for a computer, including a mode register.
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Yamamura Kimio (Tokyo JPX), An apparatus for accessing a memory.
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Suzuki Seigo (Yokohama JPX) Eguchi Seiji (Kawasaki JPX) Moriya Yoshiaki (Inagi JPX), Apparatus and method for operand fetch control.
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Kipp Donald, Apparatus and method to reduce instruction address storage in a super-scaler processor.
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Johnson William M. (San Jose CA), Data processing system with overlapped address translation and address computation.
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Ikeya Fumihiro (Kashiwa JPX), Data processor.
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Drogichen Daniel P. (West Chester PA), Device for automatic modification of ROM contents by a system selected variable.
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Mitchell Glen R. (Pine Island MN) Mustain Richard G. (Rochester MN) Peterson Jon H. (Rochester MN) Whitley Lawrence D. (Rochester MN), Directed address generation for virtual-address data processors.
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Cerutti Walter (Ivrea ITX), Electronic circuit for extending the addressing capacity of a processor.
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Pohlman ; III William B. (Los Gatos CA) Ravenel ; III Bruce W. (Sunnyvale CA) McKevitt ; III James F. (San Jose CA) Morse Stephen P. (San Francisco CA), Extended address, single and multiple bit microprocessor.
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Drogichen Daniel P. (West Chester PA), External data store memory device.
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Kraemer Alan D. (Tustin CA) Kane James A. (Santa Ana CA), Flexible addressing and sequencing system for operand memory and control store using dedicated micro-address registers l.
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Schultz Gary E. (San Juan Capistrano CA) Weidner Albert J. (Tempe AZ), Indirect address computation circuit.
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Sakamura Ken (Tokyo JPX), Instruction format with sequentially performable operand address extension modification.
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Lewis John (Tigard OR), Memory mapping system.
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Sundell Hans E. (Stockholm SEX) Egeland Terje (lvsjSEX) Johnson Sten E. (Huddinge SEX) Friman Erik B. (Stockholm SEX), Method and apparatus for determining in a computer which of a number of programs are allowed to utilize a rapid access m.
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Stettmaier Helmut (Olching DEX), Method and apparatus for modifying addresses for the memory control of a one-chip microcomputer having an externally exp.
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Egy Ronald L., Method and apparatus for setting a plurality of addresses.
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Letwin James (Kirkland WA), Method and operating system for executing programs in a multi-mode microprocessor.
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Lane John H. (Huntington Beach CA), Modulo addressing apparatus for use in a microprocessor.
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Woods William E. (Natick MA) Stanley Philip E. (Westboro MA) Lemay Richard A. (Bolton MA), Multiple length address formation in a microprogrammed data processing system.
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Kiya Nobuyuki (Hachioji JPX), Numerical control method.
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Nibby ; Jr. Chester M. (Peabody MA) Panepinto ; Jr. William (Tewksbury MA), Rotating chip selection technique and apparatus.
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Wang Bu-Chin (Saratoga CA) Daly Marita E. (El Cerrito CA), Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed.
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Buer, Mark, System and method of sharing memory by arbitrating through an internal data bus.
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Buer, Mark, System and method of sharing memory by arbitrating through an internal data bus.
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Drimak Edward G. (Johnson City NY), Vector processing.
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Mitchell Glen R. (Pine Island MN) Soltis Frank G. (Rochester MN) Hoffman Roy L. (Pine Island MN), Virtual addressing apparatus employing separate data paths for segment and offset portions of a virtual address and util.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Computer memory addressing employing base and index registers 원문보기

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Computer memory addressing employing base and index registers 원문보기

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