초록 ▼

In a scanning circuit having a plurality of cascade-connected unit circuits driven only by direct current, each unit circuit consisting of at least a pair of polarity inverting circuits, a train of output pulses shifted by a constant delay one after another depending upon the delay time proper to th

In a scanning circuit having a plurality of cascade-connected unit circuits driven only by direct current, each unit circuit consisting of at least a pair of polarity inverting circuits, a train of output pulses shifted by a constant delay one after another depending upon the delay time proper to the unit circuits, are derived from the unit circuits by applying an input pulse to the first stage of the scanning circuit.

대표청구항 ▼

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected unit circuits, each unit circuit having a first and a second polarity inverting circuits and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circu

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected unit circuits, each unit circuit having a first and a second polarity inverting circuits and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first and a second power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits; wherein said first polarity inverting circuit consists of a first and a second transistor and said second polarity inverting circuit consists of a third and a fourth transistors, each said first, second, third and fourth transistors having an input terminal and first and second output terminals and said first output terminal of each of said first and third transistors being commonly connected with one end of said first power source means, said second output terminals of said first and third transistors being connected respectively with said first output terminals of said second and fourth transistors, said second output terminals of said second and fourth transistors being connected with the other end of said first power source means; each unit circuit further including a fifth transistor having an input terminal connected with said second power source means, a first output terminal connected with one of said first output terminals of said second and fourth transistors and a second output terminal connected with one of said input terminals of said fourth transistor and said output means.