초록 ▼

A code detector for detecting the presence or absence of particular binary digital signalling codes in the digital bit stream from extension telephones of a digital PABX telephone system. The detector is connected to a telephone being monitored and receives digital data from the telephone, which dat

A code detector for detecting the presence or absence of particular binary digital signalling codes in the digital bit stream from extension telephones of a digital PABX telephone system. The detector is connected to a telephone being monitored and receives digital data from the telephone, which data may be random speech data or a signalling code. The detector consists essentially of a ROM which uses each of the data bits arriving in serial form as the least significant bits of the address for a micro-program stored in the ROM which provides the other address bits, thus causing the program to be stepped through a sequence of addresses which depend upon the sequence of the incoming data bits. For a program to end up at a specified address the ROM must receive the code which is unique in causing the program to arrive at that address. The detector then outputs a code representative of the detected code.

대표청구항 ▼

A code detector for detecting the presence or absence of particular sequences of data serial bits in a digital bit stream, comprising a memory adapted to sequentially receive said data bits, each location of said memory being programmed to contain one part of the address of two or more further locat

A code detector for detecting the presence or absence of particular sequences of data serial bits in a digital bit stream, comprising a memory adapted to sequentially receive said data bits, each location of said memory being programmed to contain one part of the address of two or more further locations in the memory, the other part of the address being provided by a bit in said serial digital bit stream to cause said memory to address successive locations dependent upon the data bit received, said memory being adapted to provide a first output signal representative of said one part of the address of two or more further locations, and a second output signal indicating when predetermined locations are reached, said output signifying the presence of a particular sequence, said first output signal being fed back to the input of said memory via an address register and being combined with the other part of the address which is fed to the input of said memory via a buffer store, said code detector further comprising clock means for timing the addressing of said successive address locations.