초록 ▼

A sample-and-hold circuit has an input terminal connected to a source of analog voltages to be stored, this terminal being connected during a sampling phase via a first switch to an output terminal and to an input of a first amplifier working into a storage capacitor by way of a second switch also c

A sample-and-hold circuit has an input terminal connected to a source of analog voltages to be stored, this terminal being connected during a sampling phase via a first switch to an output terminal and to an input of a first amplifier working into a storage capacitor by way of a second switch also closed during that phase. The capacitor is tied to one of two differential inputs of a second amplifier, the other differential input being connected to the output of the first amplifier upon closure of a third switch during a holding phase in which the first and second switches are open. A fourth switch, also closed during the holding phase, establishes a feedback path from the output of the second amplifier to the input of the first amplifier whereby the two differential inputs are energized with substantially equal voltages maintaining a certain error voltage which is smoothed by a low-pass filter or integrator in the feedback path and which appears on the output terminal with a magnitude equal to that of the source voltage. The circuit may be used in a pulse radar to lock the freqency of a local oscillator onto a variable carrier frequency.

대표청구항 ▼

A sample-and-hold circuit comprising: a first amplifier having an input and an output; a second amplifier having a pair of differential inputs and an output; an input terminal connected to a source of voltage to be stored; an output terminal permanently connected to the input of said first amplifier

A sample-and-hold circuit comprising: a first amplifier having an input and an output; a second amplifier having a pair of differential inputs and an output; an input terminal connected to a source of voltage to be stored; an output terminal permanently connected to the input of said first amplifier; a first switch inserted between said input terminal and said output terminal; a storage capacitor permanently connected to one of said differential inputs; a second switch inserted between the output of said first amplifier and said one of said differential inputs; a third switch inserted between the output of said first amplifier and the other of said differential inputs; a feedback path extending from the output of said second amplifier to the input of said first amplifier and to said output terminal; a fourth switch in said feedback path; and control means connected to said first, second, third and fourth switches for closing said first and second switches to the exclusion of said third and fourth switching during a sampling phase of an operating cycle, thereby connecting said input terminal independently of said amplifiers to said output terminal and via said first amplifier to said storage capacitor for building up a charge voltage thereon, and for closing said third and fourth switches to the exclusion of said first and second switches during a holding phase of said operating cycle, thereby feeding back an error voltage whose magnitude on the input of said first amplifier and thus on said output terminal substantially equals the magnitude of the source voltage at the end of the preceding sampling phase and whose magnitude on the output of said first amplifier and thus on said other of said differential inputs substantially balances said charge voltage.