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A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to eac

A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to each of the element sensors of the corresponding column of the array. Two “snapshots”of the scene are taken at time-displaced intervals and are compared to detect differences therebetween to eliminate background, or unchanging scene content. The individual sensors provide outputs which are injected into the aabaabababababab

대표청구항 ▼

A processor for moving target imaging of a sensed scene comprising at least one elemental area, and including: a charge transfer device including at least two stages, a first of said stages having an injector; sensor means connected to said injector corresponding to said at least one elemental area

A processor for moving target imaging of a sensed scene comprising at least one elemental area, and including: a charge transfer device including at least two stages, a first of said stages having an injector; sensor means connected to said injector corresponding to said at least one elemental area for producing an output signal in proportion to the information content of said elemental area of the sensed scene, a change of information content in said elemental area indicating movement in the sensed scene, control means for selectively producing clocking signals to advance charge packets through said at least two pair-related stages in succession and for supplying control signals to said injector to enable injection of a charge packet into the the first of said related pair of stages, said control means being selectively rendered operable to initiate said first sampling of said sensor output by enabling said injector to develop a charge packet corresponding to the level of that said first sample of said sensor output, said control means producing control signals for said injector and a first sequence of clocking signals for said first of said pair-related stages to enable the injection of said first charge packet by said injector means into said first associated stage, and said control means being selectively operable to generate a second sequence of said control signals upon initiating a second sampling of said sensor output to cause said injector to inject a corresponding second charge packet into said associated first stage while propagating said first charge packet to said second stage of said associated pair, and thereafter to generate said clocking signals at a predetermined shift cycle rate to propagate said first and second charge packets through said successive stages.