초록 ▼

The clock generator, which is shown as being a part of a data processor, includes a recirculating shift register and gate combination for deriving a set of four clock phase signals from a master clock signal. The generator also includes two gates and a D flop which form sequential circuitry. The lat

The clock generator, which is shown as being a part of a data processor, includes a recirculating shift register and gate combination for deriving a set of four clock phase signals from a master clock signal. The generator also includes two gates and a D flop which form sequential circuitry. The latter controls the shift register to impart a desired nonsymmetry to the clock signals, and to vary that symmetry, as necessary to minimize the clock cycle time and to maximize the processor operating speed. To this end, the circuitry normally makes the clock pulse widths a minimum, consistent with the processor requirements, and, on demand, doubles the widths of only those clock pulses which are actually timing the slowest processor portion, thereby lengthening only those specific clock cycles which contain the demanded widened clock pulses.

대표청구항 ▼

In clock generator apparatus including a circulating shift register portion having a master clock input connection, a shift enable connection, and a plurality of parallel output connections, said portion, in the presence of a shift enabling signal on said shift enable connection, being responsive to

In clock generator apparatus including a circulating shift register portion having a master clock input connection, a shift enable connection, and a plurality of parallel output connections, said portion, in the presence of a shift enabling signal on said shift enable connection, being responsive to a master clock signal applied to said clock input connection to circulate a logic bit among said output connections under the control of said master clock signal, thereby to produce at each of said output connections a corresponding one of a group of clock phase signals, each of which consists of a series of pulses of widths related to the master clock signal period, the improvement for imparting a desired nonsymmetry to said clock phase signals, comprising gating means having inputs connected to said output connections to receive said clock phase signals, having an output connected to said shift enable connection, and operative to apply a shift enabling signal to said shift enable connection in the presence of certain of said pulses to terminate the latter, and to suspend said application of said shift enabling signal to said shift enable connection in the presence of others of said pulses to widen the latter, and bistable means connected to receive said shift enabling signal and connected to said inputs of said gating means to cause the latter to produce said shift enabling signal in each master clock signal period following one in which the application of said shift enabling signal was suspended, thereby to limit the extent of said widening of said other pulses.