초록 ▼

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by ei

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas－user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

대표청구항 ▼

A multiprocessor system of the kind in which separate processor modules operate concurrently and cooperatively for system control and application processing, said multiprocessor system comprising, a plurality of separate processor modules, each processor module comprising a central processing unit w

A multiprocessor system of the kind in which separate processor modules operate concurrently and cooperatively for system control and application processing, said multiprocessor system comprising, a plurality of separate processor modules, each processor module comprising a central processing unit within the processor module, a separate main read-write word addressable memory within the processor module having sufficient capacity for the storage of system control and application programs and data, and a dedicated memory bus within the processor module connecting the separate main memory in the processor module exclusively to its associated central processing unit in the processor module for access to said programs and data without contention with central processing units in other processor modules, interprocessor bus means separate and distinct from an input/output system and from a memory bus and interconnecting the processor modules for direct processor module to processor module signaling and data transfer, said interprocessor bus means including, a common shared interprocessor bus, interprocessor control means in each processor module for connection that processor module to the interprocessor bus, and centralized bus controller means operatively associated with the interprocessor bus and each interprocessor control means for determining the priority of data transfers over the interprocessor bus and for controlling transmissions over the interprocessor bus, said bus controller means including, arbitration means for centrally arbitrating the priority of said data transfers and bus clock generator means for controlling the time sequence of data transfer by a processor module over the interprocessor bus, said processor module including: reading means for reading data from the associated main read/write memory of that processor module for transmission to the interprocessor bus, and writing means for writing data received from the interprocessor bus into a specied location in the association main read/write memory of that processor module, wherein said reading and writing means are effective to transfer data from the memory of a sender processor module to the memory of a receiver processor module, and wherein each processor module includes a buffer for each other processor module and also includes location pointing means for directing incoming data from an interprocessor bus to a specified location in a related buffer in the memory of a receiver processor module.