초록 ▼

A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Seco

A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

대표청구항 ▼

A process for fabricating an infrared CCD imager comprising the steps of: (a) oxidizing the surface of a monocrystalline HgCdTe body to form an oxide layer 500-1000 angstroms thick; (b) selectively removing predetermined portions of said oxide layer to form apertures therein; (c) forming suitable do

A process for fabricating an infrared CCD imager comprising the steps of: (a) oxidizing the surface of a monocrystalline HgCdTe body to form an oxide layer 500-1000 angstroms thick; (b) selectively removing predetermined portions of said oxide layer to form apertures therein; (c) forming suitable doped regions in said apertures to form junction diodes with the HgCdTe surface; (d) depositing a layer of zinc sulfide to cover the oxide-conductor composite layer; (e) depositing and patterning a channel-stop conductor on said zinc sulfide to define the CCD channel; (f) depositing and patterning a second zinc sulfide layer to overlap said channel-stop conductor; (g) depositing and patterning a first plurality of metal gates on said second zinc sulfide layer; (h) depositing a third layer of zinc sulfide to cover said gate; (i) depositing and patterning a second plurality of metal gates on said third zinc sulfide layer; (j) selectively removing portions of each zinc sulfide layer to form contact vias exposing selected gate and substrate locations; and (k) then forming conductive contacts to said exposed locations.