초록 ▼

A system for providing signals to a microprocesser-based control from which instantaneous values of speed can be computed includes a wheel-driven alternator which provides an alternating current output whose frequency varies with wheel speed. A signal processor converts this signal to a series of se

A system for providing signals to a microprocesser-based control from which instantaneous values of speed can be computed includes a wheel-driven alternator which provides an alternating current output whose frequency varies with wheel speed. A signal processor converts this signal to a series of sensor pulses whose width varies inversely with frequency. A sample pulse is supplied from the microprocessor which sets the period or length of time the sensor pulses are examined for each speed calculation of the microprocessor. The sample period pulses are AND gated with a high rate clock and also with the sensor pulses to provide a series of marker pulses marking the up and down excursions of the sensor pulses. The marker pulses occurring in each sample period are counted directly in a first counter, are supplied to a latch circuit, and from thence to an AND gate which responds to the occurrence of the first marker pulse in the sample period to connect the high rate clock pulses to a second counter for the remainder of the sample period, and to a third counter where the marker pulses act to reset the count to zero. The third counter is also connected to receive the high rate clock pulses so that it counts only the clock pulses occurring after the last marker pulse in the sample period. At the end of the sample period, the counts from all three counters are transferred to the microprocessor which uses this information to compute a value for wheel (or tire) velocity over the sample period. The system continues to provide the input counts to enable the microprocessor to calculate wheel (tire) velocity for each sample period.

대표청구항 ▼

In a skid control system for a vehicle having at least one wheel including a brake on said wheel and brake-actuating means, operator-operated means for operating said actuating means, a control element for overriding said operator-operated means, and an electronic control system including a micropro

In a skid control system for a vehicle having at least one wheel including a brake on said wheel and brake-actuating means, operator-operated means for operating said actuating means, a control element for overriding said operator-operated means, and an electronic control system including a microprocessor having means generating a series of uniform sample pulses and means producing a signal in response to decelerations in excess of a desired value for operating said control element, said deceleration-responsive means including means generating a digital signal responsive to rotational speed of said wheel: characterized in that said rotational wheel speed signal-generating means comprises sensor means including signal-processing means generating a series of pulses whose frequency varies with the rotational speed of said wheel, a digital clock producing clock pulses at a rate substantially greater than the pulse frequency of said sensor means and the frequency of said sample pulses, a first AND gate connected to receive said sample pulses and said sensor pulses to enable said sensor pulses during the period of said sample pulses, pulse-generating means receiving said sensor pulses from said first AND gate producing narrow marker pulses whenever the leading edge or the trailing edge of said sensor pulses occurs within the period of a sample pulse, a second AND gate connected to receive said sample pulses and said clock pulses and conducting said clock pulses during the period said sample pulses are present, first counter means having reset means connected to receive said marker pulses and receiving said clock pulses from said second AND gate such that said first counter means is reset with each marker pulse and said first counter means counts said clock pulses during the period of said sample pulse subsequent to receipt of the last of said marker pulses, a third AND gate connected to receive said narrow marker pulses and said clock pulses to enable clock pulses during the period of said sample pulse subsequent to receipt of said first marker pulse and a second counter connected to count said clock pulses from said third AND gate, a third counter connected to count said marker pulses, and means connecting the counts of said first, second and third counters to said microprocessor at the end of each sample period.