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High-voltage circuit for insulated gate field-effect transistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-003/353
  • H03K-017/687
  • H03F-003/16
  • H01L-029/78
출원번호 US-0036972 (1979-05-08)
우선권정보 JP-0061057 (1978-05-24)
발명자 / 주소
  • Yoshida Isao (Hinodemachi JPX) Nagata Minoru (Kodaira JPX) Ochi Shikayuki (Akishima JPX) Katto Hisao (Hinodemachi JPX)
출원인 / 주소
  • Hitachi, Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 80  인용 특허 : 2

초록

A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET bei

대표청구항

A high-voltage MOSFET (insulated gate field-effect transistor) circuit wherein n MOSFETs are connected in series by electrically connecting a drain of the m-th (1≤m≤n-1) MOSFET and a source of the (m+1)-th MOSFET, a source and gate of the first MOSFET being respectively used as a source terminal and

이 특허에 인용된 특허 (2)

  1. Nishizawa Jun-ichi (Sendai JA) Mochida Yasunori (Hamamatsu JA), Compound transistor circuitry.
  2. Yokoyama ; Kenji, Compound transistor circuitry.

이 특허를 인용한 특허 (80)

  1. Willard, Simon Edward; Ranta, Tero Tapio, AC coupling modules for bias ladders.
  2. Grimm, Michael; Chen, Jun, Adaptive cascode circuit using MOS transistors.
  3. Hur, Joonhoi; Draxler, Paul Joseph; Presti, Calogero; Cassia, Marco, Bias circuits and methods for stacked devices.
  4. Janutka William J. (West Allis WI), Bidirectional drain to drain stacked FET gating circuit.
  5. Tirdad Sowlati, Bootstrapped dual-gate class E amplifier circuit.
  6. Tirdad Sowlati, Cascode bootstrapped analog power amplifier circuit.
  7. Mauder, Anton; Hirler, Franz, Cascode circuit.
  8. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
  9. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
  10. Emsenhuber, Matthias, Circuit and method for operating the circuit.
  11. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  12. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  13. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  14. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
  15. Heijden, Mark Peter; Leenaerts, Dominicus; Apostolidou, Melina, Electronic circuit with cascode amplifier.
  16. Karl-Otto Dohnke DE; Heinz Mitlehner DE; Dietrich Stephani DE; Benno Weis DE, Electronic switching device having at least two semiconductor components.
  17. Pobanz, Carl Walter, FET active load and current source.
  18. Nunally Patrick O. (Diamond Bar CA), Fault-resistant solid-state line driver.
  19. Johnson, Joseph Herbert, Field effect transistor (FET) having fingers with rippled edges.
  20. Honda Akira (Odawara JPX), Field effect transistor circuit arrangement.
  21. Ritenour, Andrew P., Gallium nitride (GaN) device with leakage current-based over-voltage protection.
  22. Cox Mason F. (Shelby NY), High voltage amplifier.
  23. Barlow Allen R. (Pocatello ID) Petersen Corey (Pocatello ID), High voltage circuits in low voltage CMOS process.
  24. Lee, Edward K. F., High voltage current source and voltage expander in low voltage process.
  25. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., High voltage field effect transistor finger terminations.
  26. Milberger Walter E. (Severna Park MD), High voltage field effect transistor pulse apparatus.
  27. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., High voltage field effect transitor finger terminations.
  28. Isik, Tacettin, High voltage switch utilizing low voltage MOS transistors with high voltage breakdown isolation junctions.
  29. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
  30. Bolander William Joseph ; Morris Robert Leonard, Ignition timing control.
  31. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  32. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  33. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  34. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  35. Sheridan, David Charles; Dry, Robert Charles; Willis, Don, Integrated power module with improved isolation and thermal conductivity.
  36. Wu Rong-Tyan,TWX, Intelligent bias voltage generating circuit.
  37. Erskine James C. (Birmingham MI) Valeri Stephen J. (Warren MI), Internal combustion engine ignition system.
  38. Ritenour, Andrew P., Lateral semiconductor device with vertical breakdown region.
  39. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
  40. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  41. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  42. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  43. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  44. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  45. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  46. Ritenour, Andrew P., Method for on-wafer high voltage testing of semiconductor devices.
  47. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
  48. Kobayashi, Kevin Wesley; Henry, Haldane S.; Ritenour, Andrew P., Methods for fabricating high voltage field effect transistor finger terminations.
  49. Hajimiri, Seyed-Ali; Kee, Scott D.; Aoki, Ichiri, Multi-cascode transistors.
  50. Ochii Kiyofumi (Yokohama JPX) Masuda Masami (Tokyo JPX) Kondo Takeo (Yokosuka JPX), Positive feedback amplifier circuitry.
  51. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
  52. Levesque, Chris; Kobayashi, Kevin Wesley; Nadimpalli, Praveen Varma; Clark, Ricke W., Power amplifier controller.
  53. Ritenour, Andrew P.; Partyka, Paul, Power device packaging having backmetals couple the plurality of bond pads to the die backside.
  54. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
  55. Granger-Jones, Marcus, SOI switch enhancement.
  56. Granger-Jones, Marcus, SOI switch enhancement.
  57. Ritenour, Andrew P., Schottky gated transistor with interfacial layer.
  58. Weis, Rolf; Deboy, Gerald; Treu, Michael; Willmeroth, Armin; Weber, Hans, Semiconductor arrangement with active drift zone.
  59. Weis, Rolf; Treu, Michael; Deboy, Gerald; Willmeroth, Armin; Weber, Hans, Semiconductor arrangement with active drift zone.
  60. Weis, Rolf; Hirler, Franz; Feldtkeller, Martin; Deboy, Gerald; Stecher, Matthias; Willmeroth, Armin, Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices.
  61. Weis, Rolf; Hirler, Franz; Feldtkeller, Martin; Deboy, Gerald; Stecher, Matthias; Willmeroth, Armin, Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices.
  62. Weis, Rolf; Hirler, Franz; Feldtkeller, Martin; Deboy, Gerald; Stecher, Matthias; Willmeroth, Armin, Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices.
  63. Weis, Rolf; Hirler, Franz; Stecher, Matthias; Willmeroth, Armin; Deboy, Gerald; Feldtkeller, Martin, Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices.
  64. Ritenour, Andrew P., Semiconductor device having improved heat dissipation.
  65. Ritenour, Andrew P., Semiconductor device having improved heat dissipation.
  66. Ritenour, Andrew P., Semiconductor device with electrical overstress (EOS) protection.
  67. Olson, Chris, Semiconductor devices with switchable ground-body connection.
  68. Carroll, Michael; Kerr, Daniel Charles; Iversen, Christian Rye; Mason, Philip; Costa, Julio; Spears, Edward T., Semiconductor radio frequency switch with body contact.
  69. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  70. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  71. Kitazawa, Takayaki; Miyazawa, Naoyuki, Switching circuit, switching module and method of controlling the switching circuit.
  72. Kitazawa,Takayuki; Miyazawa,Naoyuki, Switching circuit, switching module and method of controlling the switching circuit.
  73. Weis, Rolf, Transistor arrangement with a first transistor and with a plurality of second transistors.
  74. Blyth,Trevor, Transistor circuits for switching high voltages and currents without causing snapback or breakdown.
  75. Kobayashi, Kevin Wesley, Transition frequency multiplier semiconductor device.
  76. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
  77. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
  78. Maoz Barak (Highland Park NJ), Variable attenuator having voltage variable FET resistor with chosen resistance-voltage relationship.
  79. Maoz Barak (Highland Park NJ), Voltage variable FET resistor with chosen resistance-voltage relationship.
  80. Vetury, Ramakrishna; Shealy, Jeffrey Blanton, Wide bandwidth radio frequency amplier having dual gate transistors.
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