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Fault tolerant computational system and voter circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
  • H03K-019/08
출원번호 US-0205935 (1980-11-12)
발명자 / 주소
  • Wensley John H. (Salem OR)
출원인 / 주소
  • August Systems (Tigard OR 02)
인용정보 피인용 횟수 : 60  인용 특허 : 2

초록

A fault-tolerant computational system having a voter circuit which receives inputs from several computational devices and produces an output in agreement with a majority of the inputs. Also included is a clock circuit for synchronizing the output of data from the computational devices so that the in

대표청구항

A fault-tolerant computation system comprising: a plurality of computational devices producing binary data output signals; and a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which ag

이 특허에 인용된 특허 (2)

  1. Ando ; Hisashige, Majority decision logic circuit.
  2. Norton David J. (Chippenham GB2) Brown Christopher R. (Chippenham GB2), Railway control signal interlocking systems.

이 특허를 인용한 특허 (60)

  1. Uebel Helmut (Leonberg DEX), 2-out-of-3 Selecting facility in a 3-computer system.
  2. Diller Robert W. (Pasadena CA), Apparatus and method employing multiple crash evaluation algorithms for actuating a restraint system in a passenger vehi.
  3. McPherson Andrew D. (Cambridge GB2), Apparatus and method for determining true data in a digital data stream from distorted data.
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  5. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  6. Bond David G. (Kent WA) Hill Todd (Tukwila WA) Weis Paul D. (Seattle WA) Woods John R. (Auburn WA), Autonomous N-modular redundant fault tolerant clock system.
  7. Hakura, Ziyad S.; Lindholm, John Erik; Kilgariff, Emmett M.; Ohannessian, Robert; Whitman, Scott R.; Bowman, James C.; Brown, Patrick R.; Cunniff, Ross A., Cull before vertex attribute fetch and vertex lighting.
  8. Hakura, Ziyad S.; Lindholm, John Erik; Kilgariff, Emmett M.; Ohannessian, Robert; Whitman, Scott R.; Bowman, James C.; Brown, Patrick R.; Cunniff, Ross A., Cull before vertex attribute fetch and vertex lighting.
  9. Blount, Harry; Shanahan, Travis; Clark, James; Guido, Dana, Data augmentation based on second-phase metadata.
  10. Maher John W. (Woodstock IL), Distributed fault isolation and recovery system and method.
  11. Ishii Kazuhiko (Hitachi JPX) Noguchi Atomi (Hitachi JPX) Gotoh Yoshimi (Hitachi JPX), Fault tolerable redundancy control.
  12. Waldie, Arthur Howard; James, Robert Ward; Canales, Timothy John; White, Michael L., Fault tolerant storage cell.
  13. Norris Joseph P., Fault tolerant synchronous clock distribution.
  14. Lam Jack F. (Endwell NY) Schmid Hermann (Binghamton NY), Fault tolerant, frame synchronization for multiple processor systems.
  15. Fulcomer, James L., Fault triggerred automatic redundancy scrubber.
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  18. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  19. Harper Richard E. (Needham MA) Lala Jaynarayan H. (Wellesley MA), Fault-tolerant parallel processing system.
  20. Lindholm, John Erik; Hakura, Ziyad S., Generating clip state for a batch of vertices.
  21. Kikuchi Toshio (Tokyo JPX), High-reliability computer system.
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  24. Christiaan Steinz H. (Hattem NLX), Logic voting-circuit.
  25. Suzuki Seigo (Tokyo JPX) Yabe Yukihiko (Yokohama JPX) Kawakami Masumi (Yokohama JPX), Majority circuit comprising binary counter.
  26. Williams Emrys John,GBX, Memory management in fault tolerant computer systems utilizing a first and second recording mechanism and a reintegrati.
  27. Lee,Chin, Memory modeling circuit with fault toleration.
  28. Suffin, A. Charles, Method and apparatus for deterministically booting a computer system having redundant components.
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  32. Kantz, Heinz; Scheck, Oliver; Metzner, Peter, Method of determining a uniform global view of the system status of a distributed computer network.
  33. Hoy Robert S. ; Grai Timothy J. ; Hozeska Robert J., Method of non-intrusive testing for a process control interface system having triply redundant remote field units.
  34. Somers, Jeffrey; Thaller, Kurt; Warchol, Nicholas, Methods and apparatus for clock management based on environmental conditions.
  35. Hall, Christopher M., Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system.
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  38. Van Driel Carel-Jan L. (Eindhoven NLX), Multiple redundant clock circuit.
  39. Smith Steven E. (Manhattan Beach CA) Murphy Kenneth J. (Canoga Park CA), Multiple-redundant fault detection system and related method for its use.
  40. Arita Setsuo (Hitachi JPX) Sato Takao (Toukai JPX), Multiplex control apparatus having middle value selection circuit.
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  45. Drake, Alan J.; KleinOsowski, AJ; Martin, Andrew K., Self-resetting, self-correcting latches.
  46. Iwase, Akihiro; Kato, Yoshiharu, Semiconductor device having test mode entry circuit.
  47. Bocci Paul M. (Roselle IL) Pietrzak ; Jr. Carl M. (Schaumburg IL) Wilson Alan L. (Hoffman Estates IL), Signal selection by statistical comparison.
  48. VanBuren,Damon A., Soft error detection and recovery.
  49. Ossfeldt Bengt E. (lvsjSEX), Stored program controlled real time system including three substantially identical processors.
  50. Nelson, Donald John; Rogoff, Stephen Forrest; Vetsch, LeRoy Ernest, System and method for three input voting.
  51. Nickolls, John R.; Nyland, Lars; Mills, Peter C.; Sugerman, Jeremy; Foley, Timothy; Fahs, Brian; Garland, Michael; Luebke, David P., Systems and methods for voting among parallel threads.
  52. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system.
  53. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system and associated method.
  54. McIver George W. (Redondo Beach CA) Marum John R. (Berkeley CA) Cho James B. (Gardena CA), Triple redundant fault-tolerant register.
  55. Kohnen, Kirk, Triple redundant self-scrubbing integrated circuit.
  56. Norman John H. (Chandler AZ), Uninterruptable fault tolerant data processor.
  57. Tang, Yangyang; Zhang, Chen-Xiong, Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it.
  58. Walter Chris J. (Columbia MD) Kieckhafer Roger M. (Lincoln NE) Finn Alan M. (Amston CT), Voter subsystem for a fault tolerant multiple node processing system.
  59. Johnson,Tyler James, Voting circuit.
  60. Mitra, Subhasish; McCluskey, Edward J., Word voter for redundant systems.
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