[특허]Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber

[미국특허] Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-015/12
출원번호	US-0129721 (1980-03-12)
발명자 / 주소	Varadi, Andrew G. Maghribi, Walid H.
출원인 / 주소	National Semiconductor Corporation
대리인 / 주소	Brown & Martin
인용정보	피인용 횟수 : 83 인용 특허 : 7

초록 ▼

A process performed by the manufacturer for testing integrated circuits (ICs) to insure better quality and higher reliability thereof and to eliminate the need for incoming inspection and board level testing by the chip customer. In the embodiment disclosed, in-process testing, wafer-probe testing, die separation, packaging, and one by one assembly line testing of the digital memory ICs for catastrophic failures all proceed according to conventional techniques. A large number of the ICs are then plugged into high-temperature, high signal integrity PC storage cards, each adapted for interconnecting the ICs in row-column arrays to form a memory board. The storage cards are mounted within an environmental chamber and are operatively coupled to corresponding PC driver cards mounted externally of the chamber. Next, accelerated dynamic burn-in of the ICs takes place. The PC storage cards are constructed to electrically isolate groups of the ICs so that if an IC in one group has a shorted input, the ICs in the remaining groups will still receive the appropriate dynamic signals to ensure burn-in thereof. Thereafter long functional/pattern testing of the ICs with continuous error logging occurs while the ICs are still mounted in the chamber. Finally the PC storage cards are removed from the chamber and those ICs which have logged either hard or soft errors are separated. The remaining good ICs are subjected to one by one short functional testing to determine compliance with data sheet specs. After quality control testing, the good ICs are shipped to the chip customer who can safely assemble them into user systems without performing the usual customer level incoming inspection and board level testing.

대표청구항 ▼

1. A process for testing a plurality of digital memory ICs comprising: plugging the ICs into PC storage cards each adapted for interconnecting the ICs in row-column arrays to form a memory board, the storage cards being constructed to have high temperature resistance and high signal integrity; loading the storage cards into an environmental chamber and operatively coupling a PC driver card to each of the storage cards, the driver cards being mounted outside the chamber and having drive electronics for enabling pattern testing of the ICs on each of the storage cards; subjecting the ICs to short duration pattern testing to verify that the ICs function in combination as a memory system; elevating the temperature within the chamber and applying dynamic signals to the ICs to accomplish accelerated dynamic burn-in thereof; and subjecting the ICs to parallel long functional testing while still in the chamber, including pattern testing of the ICs over a predetermined range of temperatures to determine the system interaction capabilities of the ICs, and logging hard and soft errors exhibited by individual ones of the ICs. 2. A process according to claim 1 wherein the ICs on each of the storage cards are separated into a plurality of groups which are electrically isolated from each other so that a short occuring in a selected one of the ICs in a selected one of the groups will not prevent burn-in of the ICs in the remaining ones of the groups. 3. A process according to claim 1 wherein during the burn-in step, the magnitude of the temperature within the chamber, the magnitude of the dynamic signals applied to the ICs, and the duration of the burn-in are correlated to provide a statistically equivalent processing of approximately 168 hours of operation at approximately 125° C. 4. A process according to claim 1 wherein the long functional testing step takes place while supply voltages applied to the ICs are varied.

이 특허에 인용된 특허 (7) 인용/피인용 타임라인 분석

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A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
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[미국특허] Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber 원문보기

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[미국특허] Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber 원문보기

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