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A community office switching system includes a three-level hierarchy of distributed processors operating in parallel with one another to control the operation of a central office matrix switch network interconnecting 1,920 ports. At the highest level, a stored-program call control processor controls

A community office switching system includes a three-level hierarchy of distributed processors operating in parallel with one another to control the operation of a central office matrix switch network interconnecting 1,920 ports. At the highest level, a stored-program call control processor controls call progression, establishing paths through the matrix switch network. At the second level, a series of special-purpose, stored-program, port control processors each service 960 ports, sensing and transmitting supervisory signals and communicating the occurrence of significant port events to the call control processor. Each port event control processor dedicates approximately 32 microseconds out of every 32 milliseconds to each of the 960 ports in time-multiplexed fashion, and hence no port can ever be locked out at the port-control-processor level. One from a series of stored programs is executed to service each port precisely one every 32 milliseconds. At the lowest level, a digital filtering processor, associated with each port control processor, samples some signals from each port once every millisecond, filters the sampled signals to give one filtered sample every four milliseconds, and stores the filtered samples for presentation to the associated port control processor once every 32 milliseconds.

대표청구항 ▼

1. An improved central office switching system comprising: a plurality of signal ports each generating sense data and responding to control data; a switching matrix interconnecting and establishing selective signal paths between said signal ports; a call control processor connecting to said mat

1. An improved central office switching system comprising: a plurality of signal ports each generating sense data and responding to control data; a switching matrix interconnecting and establishing selective signal paths between said signal ports; a call control processor connecting to said matrix and controlling the selective establishment of signal paths by said matrix; a port event processor having an instruction memory into which instructions governing the processing of sense data and the generation of control data may be placed; a sense and control data conveyance network connecting said ports and said port event processor over which sense data is conveyed from each of said ports in sequence to said port event processor and over which control data is thereafter conveyed back to the port from which the corresponding sense data originated; and timing means interconnecting said port event processor and said conveyance network for synchronizing their operation such that sense data for each individual port is conveyed to said port event processor, is processed by any instructions in said port event processor, and the control data generated by said processing is conveyed back to said individual port at regular, fixed-length intervals; whereby the one who creates instructions for inclusion in said instruction memory may assume the port event processor is processing sense data and generating control data for only one port and may rely upon such instructions being executed at regular, fixed-length intervals. 2. A switching system as recited in claim 1 which includes: a source of periodic timing signals within said timing means, said signals demarking the beginning and end of port data processing timing intervals; a port counter connecting to said source of periodic timing signals and arranged to count said signals for generating port count signals; port count signal conveyance means connecting said port counter to said sense and control data conveyance network for enabling said port count signals to determine which port has its sense data presented to and its control data received from said port event processor during each port data processing timing interval defined by said periodic timing signals; and instruction execution initiation means within said port event processor connecting to said source of periodic timing signals for initiating the execution of instructions within said port event processor instruction memory in response to said periodic timing signals. 3. A switching system in accordance with claim 2 which includes: a sense data memory within said sense and control data conveyance network: a first sense data conveyance mechanism within said sense and control data conveyance network connecting said signal ports to said sense data memory and conveying at least some sense data samples from each port into said sense data memory at a first rate of speed such that several sense data samples are taken during each of the regular, fixed-length intervals defined by said timing means; and a second sense data conveyance mechanism within said sense and control data conveyance network connecting said sense data memory to said port event processor and conveying said several sense data samples to said port event processor at a second rate of speed slower than said first rate of speed; whereby said port event processor is supplied with several time-spaced samples of at least some of the sense data for each port each time the port event processor processes the sense data for a port. 4. A switching system as recited in claim 3 which further includes: a digital filter through which at least some of said sense data samples flow and which averages adjacent sense data samples to reduce the number of sense data samples that are presented to said port event processor each time said port event processor is called upon to process the sense data for a port. 5. A switching system as recited in claim 4 wherein said digital filter has a larger number of data samples presented to it than the number of adjacent samples over which it averages and includes a selection mechanism for selecting a different adjacent subset of the data samples presented at different times, whereby said digital filter is rendered immune from resonance with incoming signal components in said sense data. 6. A switching system as recited in claim 5 wherein: said digital filter is constructed from a passive logic device having a first set of inputs to which sense data signal samples are presented, a second set of inputs to which are presented a set of signals indicating which adjacent sense data signals to select, a third input, and a binary output at which the average of the selected adjacent sense data values appears; which digital filter includes a data storage device connecting said binary output to said third input; whereby said storage device presents to said third input a previously generated average of said selected adjacent sense data values to serve as a tie breaker. 7. A switching system as recited in claim 2 wherein a port data store containing port data is also connected to said sense and control data conveyance network, and wherein said conveyance network conveys port data from said port data store to said port event processor when sense data for a signal port is conveyed to said processor and also conveys port data back from said port event processor to said port data store after the sense data for a port is processed, whereby data for each port is maintained in the port data store and is processed along with sense and control data for each signal port at regular, fixed-length intervals. 8. A switching system as recited in claim 7 which further includes: a data path for connecting the call control processor to the port data store; whereby the call control processor may sense or alter the data associated with any port. 9. A switching system as recited in claim 7 which includes: a sense data memory within said sense and control data conveyance network; a first sense data conveyance mechanism within said sense and control data conveyance network connecting said signal ports to said sense data memory and conveying at least some sense data samples from each port into said sense data memory at a first rate of speed such that several sense data samples are taken during each of the regular, fixed-length intervals defined by said timing means; and a second sense data conveyance mechanism within said sense and control data conveyance network connecting said sense data memory to said port event processor and conveying said several sense data samples to said port event processor at a second rate of speed slower than said first rate of speed; whereby said port event processor is supplied with several time-spaced samples of at least some of the sense data for each port each time the port event processor processes the sense data for a port. 10. A switching system as recited in claim 9 which further includes: a digital filter through which at least some of said sense data samples flow and which averages adjacent sense data samples to reduce the number of sense data samples that are presented to said port event processor each time said port event processor processes the sense data for a port. 11. A switching system as recited in claim 10 wherein said digital filter has a larger number of data samples presented to it than the number of adjacent samples over which it averages and includes a selected mechanism for selecting a different adjacent subset of the data samples presented at different times whereby said digital filter is rendered immune from resonance with incoming signal components in said sense data. 12. A switching system as recited in claim 11 wherein: said digital filter is constructed from a passive logic device having a first set of inputs to which sense data signal samples are presented, a second set of inputs to which are presented a set of signals indicating which adjacent sense data signals to select, a third input, and a binary output at which the average of the selected adjacent sense data values appears; and which digital filter includes a data storage device connecting said binary output to said third input; whereby said storage device presents to said third input a previously-generated average of said selected adjacent sense data values to serve as a tie breaker. 13. A switching system as recited in claim 7 wherein said port event processor contains a memory address register and a signal path over which, after having received port data from the port data store, the port event processor transfers at least a portion of said port data into said memory address register, whereby said port data is automatically processed by a series of instructions within said processor's memory selected in accordance with an address that is stored with the port data. 14. A switching system as recited in claim 2 wherein said port event processor includes a set of registers into which port sense data is placed and out of which control data is retrieved by the sense and control data conveyance network. 15. A switching system as recited in claim 14 wherein a port data store containing port data is also connected to said sense and control data conveyance network, and wherein the conveyance network conveys port data from said port data store to said registers when sense data for a signal port is conveyed to said registers and also conveys port data back from said registers to said port data store after the sense data for a port is processed, whereby data for each port is maintained in the port data store and is processed along with sense and control data for each signal port at regular, periodic intervals. 16. A switching system as recited in claim 15 which includes: a sense data memory within said sense and control data conveyance network; a first sense data conveyance mechanism within said sense and control data conveyance network connecting said signal ports to said sense data memory and conveying at least some sense data samples from each port into said sense data memory at a first rate of speed such that several sense data samples are taken during each of the regular, fixed-length intervals defined by said timing means; and a second sense data conveyance mechanism within said sense and control data conveyance network connecting said sense data memory to said port event processor and conveying said several sense data samples to said port event processor at a second rate of speed slower than said first rate of speed; whereby said port event processor is supplied with several time-spaced samples of at least some of the sense data for each port each time the port event processor porcesses the sense data for a port. 17. A switching system as recited in claim 16 which further includes: a digital filter through which at least some of said sense data samples flow and which averages adjacent sense data samples to reduce the number of sense data samples that are presented to said port event processor each time said port event processor is called upon to process the sense data for a port. 18. A switching system as recited in claim 17 wherein said digital filter has a larger number of data samples presented to it than the number of adjacent samples over which it averages and includes a selection mechanism for selecting a different adjacent subset of the data samples presented at different times, whereby said digital filter is rendered immune from resonance with incoming signal components in said sense data. 19. A switching system as recited in claim 18 wherein: said digital filter is constructed from a passive logic device having a first set of inputs to which sense data signal samples are presented, a second set of inputs to which are presented a set of signals indicating which adjacent sense data signals to select, a third input, and a binary output at which the average of the selected adjacent sense data values appears; and which digital filter includes a data storage device connecting said binary output to said third input; whereby said storage device presents to said third input a previously-generated average of said selected adjacent sense data values to serve as a tie breaker. 20. A switching system as recited in claim 15 wherein said port event processor contains a memory address register and a signal path over which, after having received port data from the port data store, the port event processor conveys at least a portion of said port data from said set of registers into said memory address register, thereby initiating the execution of a particular set of instructions. 21. A switching system as recited in claim 14 wherein said registers include at least first and second portions and said port event processor has access to one of said portions while said sense and control data conveyance network has access to at least one other of said portions, and said port event processor further includes: switching means connecting to said source of periodic timing signals and responsive to said periodic timing signals for altering the portions of said registers to which said port event processor and said network have access; whereby said network may transfer sense data into and control data out of a portion while said port event processor processes sense data in another portion. 22. A switching system as recited in claim 21 wherein said system has a master clock and wherein said sense and control data conveyance network gains access to said one other of said portions of said registers on alternate master clock cycles from when the port event processor gains access to said one portion of said registers, whereby said network and said processor do not interfere with each other or slow each other down but instead interleave their register access actions. 23. A switching system as recited in claim 22 wherein said port event processor includes a pair of processor units sharing a common instruction memory and respectively retrieving instructions from said memory on alternate master clock cycles. 24. A switching system as recited in claim 23 wherein said port event processor contains a memory address register and a signal path over which, after having received port data from the port data store, the port event processor conveys at least a portion of said port data from said set of registers into said memory address register, thereby initiating the execution of a particular set of instructions. 25. A switching system as recited in claim 2 wherein said port event processor includes a pair of processor units, sharing a common instruction memory, and further including: a master clock that synchronizes the memory access cycles of the processor units so they respectively retrieve instructions from said instruction memory on alternate master clock cycles, thereby interleaving their instruction memory accesses. 26. A switching system as recited in claim 25 which includes: a sense data memory within said sense and control data conveyance network; a first sense data conveyance mechanism within said sense and control data conveyance network connecting said signal ports to said sense data memory and conveying at least some sense data samples from each port into said sense data memory at a first rate of speed such that several sense data samples are taken during each of the regular, fixed-length intervals defined by said timing means; and a second sense data conveyance mechanism within said sense and control data conveyance network connecting said sense data memory to said port event processor and conveying said several sense data samples to said port event processor at a second rate of speed slower than said first rate of speed; whereby said port event processor is supplied with several time-spaced samples of at least some of the sense data for each port each time the port event processor processes the sense data for a port. 27. A switching system as recited in claim 26 which further includes: a digital filter through which at least some of said sense data samples flow and which averages adjacent sense data samples to reduce the number of sense data samples that are presented to said port event processor each time said port event processor is called upon to process the sense data for a port. 28. A switching system as recited in claim 27 wherein said digital filter has a larger number of data samples presented to it than the number of adjacent samples over which it averages and includes a selection mechanism for selecting a different adjacent subset of the data samples presented at different times, whereby said digital filter is rendered immune from resonance with incoming signal components in said sense data. 29. A switching system as recited in claim 28 wherein: said digital filter is constructed from a passive logic device having a first set of inputs to which sense data signals are presented, a second set of inputs to which are presented a set of signals indicating which adjacent sense data signals to select, a third input, and a binary output at which the average of the selected adjacent sense data values appears; which digital filter includes a data storage device connecting said binary output to said third input; whereby said storage device presents to said third input a previously-generated average of said selected adjacent sense data values to serve as a tie breaker. 30. A switching system as recited in claim 25 wherein a port data store containing port data is also connected to said sense and control data conveyance network, and wherein said conveyance network conveys port data from said port data store to said pair of processor units when sense data for ports is conveyed to the processor units and also conveys port data back from the processor units to the port data store after sense data for ports is processed, whereby data for each port is maintained in the port data store and is processed along with the sense and control data for each port at regular, fixed-length intervals. 31. A switching system as recited in claim 30 wherein said processor units each contain a memory address register and a signal path over which, after having received port data from the port data store, each processor unit conveys at least a portion of the data from the port data store into the processor unit's memory address register, thereby initiating the execution of a particular set of instructions. 32. A switching system as recited in claim 31 wherein each processor unit includes a set of registers into which port sense data and data from the port data store is placed and out of which control data and data directed to the port data store are retrieved. 33. A switching system as recited in claim 32 wherein the processor units and the sense and control data conveyance network gain access to said set of registers on alternate master clock cycles.