초록 ▼

The time of arrival of a constant speed moving object at a given location is calculated from data representing the time of arrival of the object at two preceeding locations and the relative physical distances between the three locations. An up-down counter counts up at a fixed frequency f1 during th

The time of arrival of a constant speed moving object at a given location is calculated from data representing the time of arrival of the object at two preceeding locations and the relative physical distances between the three locations. An up-down counter counts up at a fixed frequency f1 during the time interval of the object\s transversal of the distance between the first two locations and counts down at a pre-selected frequency f2 thereafter. The preselected frequency f2 is a function of the distances between locations and the fixed frequency f1. When the counter counts down to zero it produces an output pulse that occurs at the time the object reaches the given location. Operation of the time delay computer is independent of object speed.

대표청구항 ▼

A time delay computer means comprising: an up-down counter means, count up actuating means initiating count up from zero operation of said up-down counter at a first fixed frequency f1 in response to a first input signal, said count up actuating means comprising a first flip-flop means receiving sai

A time delay computer means comprising: an up-down counter means, count up actuating means initiating count up from zero operation of said up-down counter at a first fixed frequency f1 in response to a first input signal, said count up actuating means comprising a first flip-flop means receiving said first input signal, a fixed frequency oscillator means generating a signal of frequency f1, and a first AND gate means, said first AND gate means receiving the output of said fixed frequency oscillator means and actuating count-up operation of said up-down counter in response to an enabling signal from said flip-flop means, and count down actuating means disabling said count up actuating means and initiating count down operation of said up down counter means at a second pre-selected frequency f2 in response to a subsequently received second input signal, there being a pre-selected ratio of the time interval between said first and second input signals and the time interval between said second input signal and an output signal generated by the said up-down counter means, said ratio being a function of said second pre-selected frequency f2, said up-down counter means further generating a count down actuating means disabling signal when the counter reaches zero, said count down actuating means comprising, a second flip flop means receiving said second input signal and said count down actuating means disabling signal and providing a disabling signal to said first flip flop means, a variable frequency oscillator means generating a signal of frequency f2, and a second AND gate means, said second AND gate means receiving the output of said variable frequency oscillator means and actuating count down operation of said up-down counter means in response to an enabling signal from said second flip flop means.