초록 ▼

A microprocessor, having a memory element containing a plurality of multi-bit instruction words, an arithmetic logic (ALU) unit coupled to the memory element and responsive to at least a portion of each of the instruction words for performing data manipulations, and a controller for generating addre

A microprocessor, having a memory element containing a plurality of multi-bit instruction words, an arithmetic logic (ALU) unit coupled to the memory element and responsive to at least a portion of each of the instruction words for performing data manipulations, and a controller for generating address signals that are communicated to the memory element to cause sequential access of the instruction words, includes a storage element that interconnects certain of the signal lines that communicate the instruction words to the ALU to the controller. In response to a first predetermined instruction word the storage element receives and stores the portion of the instruction word being conducted to the ALU. In response to a second predetermined instruction word, the content of the storage element is transferred to the controller to form an address signal.

대표청구항 ▼

A circuit for sharing a microinstruction bit field to control register selection of an arithmetic logic unit and to specify a jump address, the circuit comprising: a memory element containing a plurality of addressable microinstructions, the microinstructions being addressed in response to address s

A circuit for sharing a microinstruction bit field to control register selection of an arithmetic logic unit and to specify a jump address, the circuit comprising: a memory element containing a plurality of addressable microinstructions, the microinstructions being addressed in response to address signals, the addressable microinstructions including a first field, a second field, a jump field, and a load field, at least one of the addressable microinstructions containing data in the load field corresponding to a load instruction and data in the jump field corresponding to a jump instruction, the first field selecting a data register for an arithmetic operation and containing a jump address simultaneously; an arithmetic logic unit coupled to the memory element to receive the data in the first and second fields of the addressable microinstructions, the arithmetic logic unit having a plurality of selectable data registers, the arithmetic logic unit selecting a data register in response to data in the first field of the one addressed microinstruction, the arithmetic logic unit for performing an arithmetic operation on the data contained in the selected register, the operation selected in response to data in the second field of the one addressed microinstruction; a storage element coupled to the memory element to receive the data in the first and the load fields of the addressable microinstructions and to store data contained in the first field in response to the data in the load field corresponding to a load instruction; and an address circuit coupled to the memory element and to the storage element for receiving stored data from the storage element and the data in the jump field of the addressable microinstructions, the address circuit providing address signals to the memory element, the address signals provided in a sequence in response to the absence of data in the jump field corresponding to a jump instruction, address signals corresponding to the received stored data in response to the data in the jump field corresponding to a jump instruction.