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A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitri

A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.

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The method for providing multilevel interconnections for an integrated circuit comprising the steps of: providing a first patterned layer of interconnect metallurgy on the surface of a semiconductor substrate passivated with an oxide of silicon; blanket depositing a layer of silicon nitride over sai

The method for providing multilevel interconnections for an integrated circuit comprising the steps of: providing a first patterned layer of interconnect metallurgy on the surface of a semiconductor substrate passivated with an oxide of silicon; blanket depositing a layer of silicon nitride over said substrate; photolithographically defining overlap via holes only through said silicon nitride layer to expose portions of said first patterned layer where interlevel contacts are desired; blanket depositing a layer of organic dielectric material over said substrates said organic dielectric layer being thicker than said silicon nitride layer; photolithographically defining oversized via holes, larger than said overlap via holes, in said organic dielectric layer to expose said overlap via holes and to re-expose said portions of said first patterned layer; and depositing a second patterned layer of interconnection metallurgy over said substrate to form continuous interconnection segments contacting said first patterned layer through said overlap and oversized via holes and passing over at least portions of said organic dielectric layer and said silicon nitride layer.