초록 ▼

This device incorporates a photosensitive (1) constituted by a matrix of photosensitive points. Each photosensitive point has a charge reading diode D1. Metallic connections (C1 to C4) connect the reading diodes of the same column to a single diode (D2), followed by a grid G2 raised to a constant po

This device incorporates a photosensitive (1) constituted by a matrix of photosensitive points. Each photosensitive point has a charge reading diode D1. Metallic connections (C1 to C4) connect the reading diodes of the same column to a single diode (D2), followed by a grid G2 raised to a constant potential (V2). The operation of the device involves the repetition of two stages, i.e. stage T1 and stage T2. During stage T1 parasitic charges, due for example to too intense illumination, are transferred from diodes D1 to diodes D2 and are removed by a diode (D5). During stage T2 the signal charges stored by the points of one line of the matrix are transferred into a memory and then into a charge transfer read register (R2). The register reads these charges during the following stages T1 and T2 until the time when the register receives the charges corresponding to the reading of the following line.

대표청구항 ▼

A photosensitive device read by charge transfer, wherein it has n lines of m photosensitive points, each photosensitive point being constituted by the integration of a semiconductor substrate of an MOS capacitor (CO), having a grid G0 common to the points of the same line and a reading diode D1 sepa

A photosensitive device read by charge transfer, wherein it has n lines of m photosensitive points, each photosensitive point being constituted by the integration of a semiconductor substrate of an MOS capacitor (CO), having a grid G0 common to the points of the same line and a reading diode D1 separated from grid G0 by a screen grid G1 raised to a constant potential (V1), m metallic connections (C1 . . . Cm) connecting in parallel n diodes belonging to different lines; m diodes D2 integrated on to the same semiconductor substrate to which lead the m metallic connections, said diodes being followed by a grid G2 raised to a constant potential (V2); removing means on a diode (D5) of the charges accumulated on diodes D1 and D2 during each time interval when none of the grids G0 is at zero; at least one shift register (R1) making it possible to periodically zero each grid G0 and remove the signal charges on diodes D1, and diodes D2; means ensuring the transfer of the signal charges arriving beneath diodes D2 to a charge transfer read register (R2) with m parallel inputs and a series output.