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Substrate with multiple type connections 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/09
  • H05K-001/18
출원번호 US-0328889 (1981-12-09)
발명자 / 주소
  • Marks Robert (South Burlington VT) Phelps
  • Jr. Douglas W. (Burlington VT) Ward William C. (Burlington VT)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 68  인용 특허 : 2

초록

A novel substrate is disclosed which can mount either flip-chip solder bonded IC chips or wire bonded chips, or both chips, or a single chip having both solder bonds and wire bonds is disclosed. The substrate has an array of solder pads which will accept solder bonds. Those pads which are to be used

대표청구항

A package for semiconductor integrated circuits comprising: a substrate having input/output means; a plurality of solder pads on said substrate; at least one integrated circuit chip having its back surface attached to said substrate in a face-up configuration with contact pad metal adapted to receiv

이 특허에 인용된 특허 (2)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  2. Kubota Kanemitsu (Suwa JPX), Electronic table calculator using liquid crystal display.

이 특허를 인용한 특허 (68)

  1. Bertolet Allan ; Fiore James ; Gramatzki Eberhard, Chip design process for wire bond and flip-chip package.
  2. Faraci Tony ; DiStefano Thomas H. ; Smith John W., Connecting multiple microelectronic elements with lead deformation.
  3. Tony Faraci ; Thomas H. Distefano ; John W. Smith, Connecting multiple microelectronic elements with lead deformation.
  4. Smith John W. ; DiStefano Thomas H., Connection components with rows of lead bond sections.
  5. James M. Wark, Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  6. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  7. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  8. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  9. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  10. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Faraci Tony (Georgetown TX), Fan-out semiconductor chip assembly.
  11. DiStefano Thomas H. ; Smith John W. ; Faraci Tony, Fan-out semiconductor chip assembly.
  12. Distefano Thomas ; Smith John W. ; Faraci Anthony B., Fixtures and methods for lead bonding and deformation.
  13. Distefano Thomas ; Smith John W. ; Faraci Anthony B., Fixtures and methods for lead bonding and deformation.
  14. Smith John W. ; Haba Belgacem, Flexible lead structures and methods of making same.
  15. Smith, John W.; Haba, Belgacem, Flexible lead structures and methods of making same.
  16. Shiffer,Stephen R., Flip chip metal bonding to plastic leadframe.
  17. Go Tiong C. (El Toro CA), High-density electronic modules-process and product.
  18. Kida, Susumu; Usami, Hayato; Aoki, Hideji, Highly reliable hermetically sealed package for a semiconductor device.
  19. Sakamoto,Noriaki; Kobayashi,Yoshiyuki; Sakamoto,Junji; Mashimo,Shigeaki; Okawa,Katsumi; Maehara,Eiju; Takahashi,Kouji, Hybrid integrated circuit device.
  20. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.
  21. Osaki Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Sasaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Interboard connection terminal and method of manufacturing the same.
  22. Carlommagno William D. (Redwood City CA) Cummings Dennis E. (Placerville CA) Gliga Alexandru S. (San Jose CA), Interconnection of electronic components.
  23. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  24. Perlman Stanley M. (Northbrook IL), Lead frame with aluminum rivets.
  25. Corisis David J., Leads under chip IC package.
  26. Corisis, David J., Leads under chip IC package.
  27. Corisis,David J., Leads under chip IC package.
  28. Corisis David J., Leads under chip in conventional IC package.
  29. Corisis David J., Leads under chip in conventional IC package.
  30. Corisis David J., Leads under chip in conventional IC package.
  31. David J. Corisis, Leads under chip in conventional IC package.
  32. Pesavento Philip V. (Manhattan Beach CA), Method for connecting leadless chip package.
  33. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.
  34. Osaka Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Susaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Method of manufacturing an interboard connection terminal.
  35. Trevison Robert L. (Spokane WA) McKee William E. (Coeur D\Alene ID) Hunnel Larry B. (Otis Orchards WA), Method of producing a jumper chip for semiconductor devices.
  36. Corisis, David J., Methods for leads under chip in conventional IC package.
  37. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  38. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  39. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  40. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  41. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  42. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  43. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  44. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  45. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  46. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  47. DiStefano Thomas H. ; Smith John W., Microelectronic assemblies with multiple leads.
  48. DiStefano Thomas H. ; Smith John W., Microelectronic assemblies with multiple leads.
  49. DiStefano, Thomas H.; Smith, John W., Microelectronic assemblies with multiple leads.
  50. Fjelstad Joseph, Microelectronic connector with planar elastomer sockets.
  51. Fjelstad, Joseph, Microelectronic connector with planar elastomer sockets.
  52. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  53. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  54. Smith John W. ; Distefano Thomas H., Microelectronic element bonding with deformation of leads in rows.
  55. DiStefano Thomas H. ; Smith John W., Microelectronic mounting with multiple lead deformation and bonding.
  56. Distefano Thomas H. ; Smith ; Jr. John W., Microelectronics unit mounting with multiple lead bonding.
  57. John W. Smith ; Belgacem Haba, Multi-layer substrates and fabrication processes.
  58. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
  59. Matsuda,Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.
  60. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  61. Grabbe Dimitry G. (Middletown PA), Semiconductor chip carrier system.
  62. Sakamoto,Noriaki; Kobayashi,Yoshiyuki; Sakamoto,Junji; Mashimo,Shigeaki; Okawa,Katsumi; Maehara,Eiju; Takahashi,Kouji, Semiconductor device and semiconductor module.
  63. DiStefano,Thomas H.; Smith,John W.; Faraci,Tony, Semiconductor package with heat sink.
  64. Sakamoto,Noriaki; Kobayashi,Yoshiyuki; Sakamoto,Junji; Mashimo,Shigeaki; Okawa,Katsumi; Maehara,Eiju; Takahashi,Kouji, Sheet-like board member and method of manufacturing a semiconductor device.
  65. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  66. Lo, Randy H. Y.; Ho, Tzong-Da; Wu, Chi-Chuan, Stacked multi-chip package structure with on-chip integration of passive component.
  67. Paul Davis Bell, Structure and method for probing wiring bond pads.
  68. Jomaa, Houssam W.; Bchir, Omar J.; Shah, Milind P.; Aldrete, Manuel; Kim, Chin-Kwan, Surface finish on trace for a thermal compression flip chip (TCFC).
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