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Scheduling device operations in a buffered peripheral subsystem 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0241322 (1981-03-06)
발명자 / 주소
  • Fry Scott M. (Tucson AZ) Hempy Harry O. (Tucson AZ) Kirkpatrick Charles R. (Tucson AZ) Kittinger Bruce E. (Fort Collins CO)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 34  인용 특허 : 3

초록

Data transfers between respective buffer segments and data source-sinks, such as peripheral data storage devices, are scheduled as a series of transfers based upon most recent, next most recent, to the least recent usage of the buffer segments by a utilization device. A list of segments ordered by s

대표청구항

The machine-implemented method of operating a storage subsystem having a data buffer with a plurality of buffer data storage spaces and being connected to and shared by a plurality of data storage devices, such buffer data storage spaces being selectively allocatable to said devices; the method incl

이 특허에 인용된 특허 (3)

  1. Franaszek Peter Anthony (Ossining NY), Apparatus for reordering the sequence of data stored in a serial memory.
  2. Desyllas ; Peter Leo Lawrence ; Jones ; John Austin ; Procter ; Brian John, Hierarchical data store with look-ahead action.
  3. Dijkstra Edsger W. (Nuenen (NB) NL), Segment replacement mechanism for varying program window sizes in a data processing system having virtual memory.

이 특허를 인용한 특허 (34)

  1. Johnson,Mark C.; Okbay,Bitwoded; Moy,Andrew; Kuo,Lih Chung, Apparatus, system, and method for managing errors in prefetched data.
  2. Case Douglas R. (San Jose CA) Conner Watson M. (Atherton CA), Cache-effective sort string generation method.
  3. Berman Ari P. (Ashland MA), Continuous data transfer system.
  4. Mapp, Glenford Ezra; Hodges, Stephen John; Roberts, Derek Edward; Pope, Steven Leslie, Data transfer, synchronising applications, and low latency networks.
  5. Hirose Fumiyasu,JPX, Data transferring buffer.
  6. Bauman, Mark Linus; Cernohous, Bob Richard; Hofer, Kent L.; Kasperski, John Charles; Simonson, Steven John; Weeks, Jay Robert, Determining on demand right size buffering within a socket server implementation.
  7. Hunter Dan A. (875 S. Bermont Dr. Lafayette CO 80026) Opperman Lawrence F. (6407 S. Kline st. Littleton CO 80127) Gooras George (1439 Lefthand Dr. Longmont CO 80501), Early end of tape sensing for a cache buffered tape drive.
  8. Wing Malcolm J. ; D'Souza Godfrey P., Gated store buffer for an advanced microprocessor.
  9. Hamstra James R. (Plymouth MN) Hanson Merlin L. (Arden Hills MN), Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory.
  10. Ming-Syan Chen ; Kun-Lung Wu ; Philip Shi-Lung Yu, Index allocation for data broadcasting.
  11. Berman Ari P. (Ashland MA), Interrupt driven multi-buffer DMA circuit for enabling continuous sequential data transfers.
  12. Hartung Michael H. (Tucson AZ) Nolta Arthur H. (Tucson AZ) Reed David G. (Tucson AZ) Tayler Gerald E. (Tucson AZ), Load balancing in a multiunit system.
  13. Gaylord Jeremy, Method and apparatus for adjusting the buffering characteristic in the pipeline of a data transfer system.
  14. Gaylord Jeremy, Method and apparatus for adjusting the buffering characteristic in the pipeline of a data transfer system.
  15. DuLac Keith B. (Derby KS) Weber Bret S. (Wichita KS), Method and apparatus for controlling data transfers through multiple buffers.
  16. Johnson, Stephen B.; Hoglund, Timothy E.; Kendall, Guy W., Method and apparatus for processing chain messages (SGL chaining).
  17. McNutt, Bruce, Method and apparatus for providing efficient management of least recently used (LRU) algorithm insertion points corresponding to defined times-in-cache.
  18. Findley Gerald I. (Tucson AZ) Yu Wellington C. (San Jose CA), Method and apparatus which allows the working storage to be reconfigured according to demands for processing data input.
  19. Liu Peichun Peter ; Branson Brian David, Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per.
  20. Bauman,Mark Linus; Cernohous,Bob Richard; Hofer,Kent L.; Kasperski,John Charles; Simonson,Steven John; Weeks,Jay Robert, Method for determining on demand right size buffering within a socket server implementation.
  21. Frey, Amy L.; Pielli, Shane D., Method for insuring data integrity for mirrored independently accessible memory devices.
  22. Hamstra James R. (Plymouth MN) Swenson Robert E. (Mendota Heights MN), Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory.
  23. Fleischmann, Marc; Anvin, H. Peter, Restoring processor context in response to processor power-up.
  24. Talluri Madhusudhan ; Pease Marshall C., System and method for remote buffer allocation in exported memory segments and message passing between network nodes.
  25. Fleischmann, Marc; Anvin, H. Peter, System and method for saving and restoring a processor state without executing any instructions from a first instruction set.
  26. Hostetter, David G.; McCallister, Ryan P., System and method for storing data with host configuration of storage media.
  27. Tal Nir,ILX ; Cohen Ron,ILX ; Collin Zeev,ILX, System for dynamically changing the length of transmit and receive sample buffers utilizing previous responding to an i.
  28. Poisner David I., System for programming peripheral with address and direction information and sending the information through data bus or.
  29. Motoyama, Satoru, Temporary storage of communications data.
  30. Kelly, Edmund; Cmelik, Robert; Wing, Malcolm, Translated memory protection.
  31. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  32. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  33. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  34. Kelly, Edmund J.; Cmelik, Robert F.; Wing, Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
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