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A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directi

A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device. A control circuit generates timing and switching signals such that, during a first bus cycle a first m-bit data word from the input/ouput device is stored in the register, and during a second bus cycle a second m-bit data word from the input/output device is transferred directly via the buses to the memory device and, also, the first m-bit data word, stored in the register, is transferred to the memory device. For transfer of a data word from the memory device to the input/output device, during a first bus cycle m bits of data are transferred directly via the buses to the input/output device and, also, the following m bits are stored in the register, and during a second bus cycle the following m bits are transferred to the input/output device.

대표청구항 ▼

An information transferring apparatus comprising: a first unit in which m-bit information is manipulated as a unit of handling, a first bus consisting of m bit signal lines, which is coupled to said first unit, a second unit in which 2 m-bit information is manipulated as a unit of handling, a second

An information transferring apparatus comprising: a first unit in which m-bit information is manipulated as a unit of handling, a first bus consisting of m bit signal lines, which is coupled to said first unit, a second unit in which 2 m-bit information is manipulated as a unit of handling, a second bus consisting of 2 m bit signal lines, which is coupled to said second unit, means for temporarily storing m bits of information, an information transfer circuit for transferring information between said first and second units, and coupled to said first bus, said second bus and said storing means, and a control circuit for controlling said information transfer circuit, and coupled to said first unit, said second unit, said storing means and said information transfer circuit, said control unit designating said second unit to send out 2 m-bit information to said second bus and controlling said information transfer circuit such that first m bits of said 2 m-bit information on said second bus are transferred to said storing means to be stored therein and at the same time the remaining m bits of said 2 m-bit information on said second bus are transferred via said first bus to said first unit and, thereafter, the stored m bits of information in said storing means are transferred via said first bus to said first unit, and said control unit designating said first unit to send out at least twice m-bit information to said first bus and controlling said information transfer circuit such that first m-bit information on said first bus is stored in said storing means, followed by transfer of the next m-bit information on said first bus via said second bus to said second unit and at the same time by transfer of the stored m-bit information from said storing means via said second bus to said second unit.