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A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a n

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

대표청구항 ▼

A data processing system comprising a data processing unit and a memory system including a plurality of addressable memory controllers, each controller for controlling the operation of a number of memory modules and said controllers being coupled in common to a bus for receiving memory commands and

A data processing system comprising a data processing unit and a memory system including a plurality of addressable memory controllers, each controller for controlling the operation of a number of memory modules and said controllers being coupled in common to a bus for receiving memory commands and data from said data processing unit, each memory command including a code specifying the type of operation to be performed by the controller specified by said command and each memory controller including: a control section coupled to said bus, said section comprising: first circuit means having a plurality of input terminals and a corresponding plurality of output terminals, said input terminals being selectively prewired to said output terminals for generating a first multibit binary code at said output terminals designating the type of design used in constructing said each controller; second circuit means having a plurality of input terminals and a corresponding number of output terminals, said input terminals being selectively prewired to said output terminals for generating a second multibit binary code at said output terminals designating the hardware revision of each said controller; and decode circuit means coupled to said bus, said decode circuit means being operative in response to a first diagnostic predetermined type of memory command to generate a first output signal; and a multibit identification register operatively coupled to said bus, said identification register including at least one control terminal coupled to said decode circuit means and a number of input terminals, a first group of said number of input terminals being connected to said output terminals of said first circuit means and a second group of said number of input terminals being connected to said output terminals of said second circuit means, said register being conditioned by said output signal to apply said first and second multibit binary codes to said bus for transfer to said data processing unit for enabling selection of diagnostic test and verification routines for testing said each controller.