초록 ▼

With this circuit arrangement a plurality of control commands can be inputted into a microcomputer system by means of only a single input channel and the microprocessor is relieved of the operation of scanning the peripherals for detecting the presence of control commands. By means of a release or e

With this circuit arrangement a plurality of control commands can be inputted into a microcomputer system by means of only a single input channel and the microprocessor is relieved of the operation of scanning the peripherals for detecting the presence of control commands. By means of a release or enabling signal the microprocessor signals its preparedness for receiving interruptions, and the release or enabling signal activates a scanning and comparator unit arranged between an interrupt requirement input of the microprocessor and a peripheral unit. Thereafter the scanning and comparator unit scans control command transmitters grouped together in the peripheral unit and characterized by an address and compares the switching state thereof with a switching state which is stored under the same address. If the two switching states are different, there is generated an interrupt requirement or requisition and the stored switching state is adapted to the switching state of the control command transmitter.

대표청구항 ▼

A microcomputer system comprising: a microcomputer containing: at least one random-access memory storing data bits in related, addressable storage locations; a read-only memory; a microprocessor; an address bus, a data bus including at least one data line, and a control bus including at least one co

A microcomputer system comprising: a microcomputer containing: at least one random-access memory storing data bits in related, addressable storage locations; a read-only memory; a microprocessor; an address bus, a data bus including at least one data line, and a control bus including at least one control line; each said address bus, said data bus and said control bus operatively interconnecting said microprocessor, said at least one random-access memory and said read-only memory; a parallel input-output interface component; conductor means and an input-output bus including a data input line, a data output line and a clock signal line; said address bus, said input-output bus and said conductor means operatively interconnecting said microprocessor and said parallel input-output interface component; a circuit arrangement for inputting control commands into said microcomputer and comprising: conductor means; a DMA component including an address register; said DMA component being connected by said address bus to the microprocessor, the parallel input-output interface component, the read-only memory, and the at least one random-access memory: said DMA component being further connected by said input-output bus to said microprocessor and said parallel input-output interface component, and by said conductor means of said circuit arrangement to said microprocessor; said input-output interface component having an interrupt request input and a DMA operation release output; said DMA component having a DMA request input and a DMA receipt output; a comparator connected to said input-output interface component via said interrupt request input and said DMA operation release output thereof and to said DMA component via said DMA request input and said DMA receipt output thereof; said microcomputer generating a DMA operation release signal which is transmitted to said comparator via said DMA operation release output of said input-output interface component and by said comparator to said DMA request input of said DMA component in order to initiate a DMA operation; a peripheral unit connected to said data input line of said input-output bus; said peripheral unit comprising a group of control command transmitters and a group of addressable storage cells; each one of said control command transmitters being operatively associated with a related one of said addressable storage cells; each said control command transmitter generating an initial control command which is stored in a related one of the addressable storage locations of said random-access memory of the microcomputer and in said related addressable storage cell as an initial data bit; each said control command transmitter, in response to an externally applied command signal, generating an instantaneous control command which is transmitted to said related addressable storage cell, replaces said initial data bit stored therein and, in turn, is stored therein as an instantaneous data bit; said comparator having a first input connected to the data input line of said input-output bus and having a second input; said comparator containing a read-write memory connected to said address bus and to said at least one control line of said control bus; said read-write memory contained in said comparator comprising a predetermined number of addressable storage locations; said read-write memory having a data input connected to said at least one data line of said data bus in order to store said initial data bit in a related one of said addressable storage locations; said read-write memory further having a data output connected to said second input of said comparator; said address register of said DMA component sequentially placing on said address bus a plurality of addresses, each of which addresses serves to address the related one of said addressable storage cells, the related one of said addressable storage locations in said read-write memory contained in said comparator and the related one of said addressable storage locations in said at least one random-access memory of said microcomputer; said comparator, during said DMA operation, receiving at said first input thereof via said data input line of said input-output bus the instantaneous data bit stored in the addressed storage cell and receiving at said second input thereof from said data output of said read-write memory said initial data bit stored at the addressed storage location thereof and comparing said instantaneous data bit and said initial data bit; said comparator, in the case of equality of the instantaneous data bit and the initial data bit, continuing to transmit said DMA operation release signal to said DMA request input of said DMA component and to compare the instantaneous data bit and the initial data bit associated with a further address of said plurality of addresses by which there is addressed a further one of the related addressable storage cells, a further one of the related storge locations in said read-write memory and a further one of the related storage locations in said at least one random-access memory; and said comparator, in the case of inequality of the instantaneous data bit and the initial data bit, generating and transmitting an interrupt request signal to said microprocessor via said interrupt request input of said input-output interface component and blocking said sequentially placing of a further address on said address bus, whereby said microprocessor, during an interrupt operation thereof, reads said instantaneous data bit, which is associated with the addressed storage cell and which is present on said data input line of said input-output bus, and writes said instantaneous data bit into the addressed storage location of said random-access memory of said microcomputer and into the addressed storage location of said read-write memory contained in said comparator via the at least one data line of said data bus, and the microprocessor, after completion of the interrupt operation, terminates said DMA operation release signal and thereby said DMA operation.