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Automatic adjustment of the quantity of prefetch data in a disk cache operation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/06
  • G06F-013/00
출원번호 US-0270750 (1981-06-05)
발명자 / 주소
  • Dixon Jerry D. (Boca Raton FL) Marazas Gerald A. (Boca Raton FL) McNeill Andrew B. (Boca Raton FL) Merckel Gerald U. (Delray Beach FL)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 47  인용 특허 : 9

초록

When transferring data to a cache memory from an attachment data storage device, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. The average quantity of data transferred to the cache memory in each operation can

대표청구항

A data processing system comprising at least one memory unit for storing a plurality of blocks of data each including n data records where n is a positive integer, a cache memory for storing a portion of the data stored in said memory unit, a host processor for requesting data stored in said memory

이 특허에 인용된 특허 (9)

  1. Gannon Patrick M. (Poughkeepsie NY) Liptay John S. (Rhinebeck NY), Cache bypass control for operand fetches.
  2. Kobayashi Yoshiuki (Kokubunji JPX) Rokutanda Takashi (Iachikawa JPX), Cache memory control system.
  3. Schmidt Carson T. (Poway CA), Cache memory having a variable data block size.
  4. Taylor ; Donald R. ; Parmet ; Arthur A., Control store system and method for storing selectively microinstructions and scratchpad information.
  5. Brown Lewis W. (Boca Raton FL) Chisholm Douglas R. (Delray Beach FL) Dixon Jerry D. (Boca Raton FL), Data processor input/output controller.
  6. Hawley Kenneth R. (Ventura CA), Dynamic disk buffer control unit.
  7. Desyllas ; Peter Leo Lawrence ; Jones ; John Austin ; Procter ; Brian John, Hierarchical data store with look-ahead action.
  8. Bayliss John A. (Portland OR) Peterson Craig B. (Portland OR) Wilde Doran K. (Aloha OR), Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor.
  9. Joyce Thomas F. (Burlington MA) Holtey Thomas O. (Newton Lower Falls MA) Panepinto ; Jr. William (Tewksbury MA), Word oriented high speed buffer memory system connected to a system bus.

이 특허를 인용한 특허 (47)

  1. Fair, Robert L., Adaptive file readahead based on multiple factors.
  2. Fair, Robert L., Adaptive file readahead technique for multiple read streams.
  3. Rosenfeld Philip L. (Briarcliff Manor NY), Apparatus and method for controlling storage access in a multilevel storage system.
  4. Bozman Gerald P. (Oakland NJ), Arbitral dynamic cache using processor storage.
  5. Matsunami Naoto,JPX ; Yoshida Minoru,JPX ; Miyazawa Shoichi,JPX ; Oeda Takashi,JPX ; Honda Kiyoshi,JPX ; Ohno Shuji,JPX, Array disk controller for grouping host commands into a single virtual host command.
  6. Macon ; Jr. James F. (Boynton Beach FL) Ong Shauchi (San Jose CA) Shih Feng-Hsien W. (Hsien-Chu TWX), Asynchronous read-ahead disk caching using multiple disk I/O processes adn dynamically variable prefetch length.
  7. Blount Michelle K. (Tucson AZ) Clark Connie M. (Tucson AZ) Harding Warren B. (Tucson AZ) Tang Horace T. S. (Tucson AZ), Batching data objects for recording on optical disks with maximum object count.
  8. Steely ; Jr. Simon C. (Hudson NH) Ramanujan Raj K. (Leominster MA) Bannon Peter J. (Acton MA) Beach Walter A. (Bedford MA), Cache with at least two fill rates.
  9. Schafer Bruce W. ; Teeters Jeffrey W. ; Chweh Mark C. ; Lee David A. ; O'Connell Daniel P. ; Ramanathan Gowri, Caching apparatus and method for enhancing retrieval of data from an optical storage device.
  10. Defouw, Richard J.; Sutton, Alan; Korngiebel, Ronald W., Caching method for selecting data blocks for removal from cache based on recall probability and size.
  11. Genduso Thomas Basilio ; Vanderslice Edward Robert, Computer system having cache prefetching amount based on CPU request types.
  12. Easton Malcolm C. (San Jose CA) Howard John H. (Pittsburgh PA), DASD cache block staging.
  13. Sakai Naohumi (Yokohama JPX) Tsuchida Masashi (Tokyo JPX) Ohmachi Kazuhiko (Kawasaki JPX) Imai Yasuhiro (Hadano JPX) Honma Toshio (Yokohama JPX), Data I/O transaction method and system.
  14. Kobayashi Yoshiyuki (Kodaira JPX) Yamagami Nobuhiko (Kunitachi JPX) Kihara Jyun-ichi (Fuchu JPX), Data prefetch apparatus.
  15. Omura Takeshi (Kyoto JPX) Hirota Teruto (Moriguchi JPX) Asai Rieko (Hirakata JPX), Data providing device, file server device, and data transfer control method.
  16. Yamagami Kenji (Kanagawa-ken JPX) Yamamoto Akira (Sagamihara JPX) Satoh Takao (Sagamihara JPX), Data transfer apparatus and method for data processing system.
  17. Wang, Ming Y.; Thelin, Gregory B., Disk drive adjusting read-ahead to optimize cache memory allocation.
  18. Wang, Ming Y., Disk drive employing thresholds for cache memory allocation.
  19. Chen,Baohua; Wong,Kimchung Arthur; Zhou,Zhinan, Dynamic PCI-bus pre-fetch with separate counters for commands of commands of different data-transfer lengths.
  20. Sathish, Vijay; Chou, Yuan, Dynamically adjusting the hardware stream prefetcher prefetch ahead distance.
  21. Simpson, III,Cecil R., Efficient command delivery and data transfer.
  22. Orbits David A. (Redmond WA) Abramson Kenneth D. (Seattle WA) Butts ; Jr. H. Bruce (Redmond WA), Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses.
  23. Chuang Chiao-Mei (Briarcliff Manor NY) Matick Richard E. (Peekskill NY) Tong Fred T. (Hopewell Junction NY), Functional cache memory chip architecture for improved cache access.
  24. Sathish, Vijay, Hardware stream prefetcher with dynamically adjustable stride.
  25. Hoshino Masayuki (Odawara JPX) Hayami Haruo (Yokohama JPX), Information retrieval control system with input and output buffers.
  26. Hite, Thomas D.; Barber, Ronald W.; Partridge, Charles W.; Lee, Mark R.; McGrane, William B.; Myer, Aaron L.; Lewno, Mark S., Internet control system communication protocol, method and computer program.
  27. Barrett Gerald G. (Austin TX) Pasha Syed Z. (Austin TX) Shaheen-Gouda Amal A. (Austin TX), Memory disk accessing apparatus.
  28. Goodwin Paul M. (Littleton MA) Tatosian David A. (Stow MA) Smelser Donald (Bolton MA), Memory stream buffer with variable-size prefetch depending on memory interleaving configuration.
  29. Hefty, Mark Sean; Coffman, Jerrie L., Method and system for communicating between memory regions.
  30. Hefty, Mark Sean; Coffman, Jerrie L., Method and system for communicating between memory regions.
  31. Hefty, Mark Sean; Coffman, Jerrie L., Method and system for communicating between memory regions.
  32. Hefty, Mark Sean; Coffman, Jerrie L., Method and system for communication between memory regions.
  33. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache.
  34. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache using multiple data structures.
  35. Brent Cameron Beardsley ; Michael Thomas Benhase ; Joseph Smith Hyde ; Thomas Charles Jarvis ; Douglas A. Martin ; Robert Louis Morton, Method and system for staging data into cache.
  36. Kase Hiroshi,JPX ; Hamai Shinji,JPX ; Morioka Yoshihiro,JPX, Method for transmitting data, and apparatus for transmitting data and medium.
  37. Christopher ; Jr. Kenneth W. (Lighthouse Point FL) Feigenbaum Barry A. (Boca Raton FL) Kim Jin (Boca Raton FL) Love Douglas C. (Delray Beach FL), Method of rapidly opening disk files identified by path names.
  38. Hopkins Charles H., Prefetching variable length data.
  39. Mark A. Gaertner ; Joseph L. Wach, Rotationally optimized seek initiation.
  40. Yuji Kawahara JP, Storage device.
  41. Stratton William (Malvern PA) Wellington Carol (Berwyn PA), System and method for accessing a cache memory which is located in the main memory of a large data processing system.
  42. Vishlitzky Natan ; Ofek Yuval ; Kopylovitz Haim, System and method for caching information in a digital data storage subsystem.
  43. Vishlitzky Natan ; Kopylovitz Haim, System and method for determining what position in cache memory to store data elements.
  44. Jost Larry T., System for automatically and continuously tuning tunable parameters by setting tuning mechanism to tune a next tunable.
  45. Benhase Michael Thomas ; Burton David Alan ; Heyman Marshall ; McCauley John Norbert ; Morton Robert Louis, System for concurrent cache data access by maintaining and selectively merging multiple ranked part copies.
  46. Benhase Michael Thomas ; Burton David Alan ; Heyman Marshall ; McCauley John Norbert ; Morton Robert Louis, System for concurrent cache data access by maintaining and selectively merging multiple ranked part copies.
  47. Hasenplaugh, William; Emer, Joel; Fossum, Tryggve; Jaleel, Aamer; Steely, Simon, Technique for controlling computing resources.
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