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Systolic array apparatuses for matrix computations 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0494659 (1983-05-16)
발명자 / 주소
  • Kung Hsiang-Tsung (Pittsburgh PA) Leiserson Charles E. (Pittsburgh PA)
출원인 / 주소
  • Carnegie-Mellon University (Pittsburgh PA 02)
인용정보 피인용 횟수 : 56  인용 특허 : 9

초록

A systolic array system of inner product step processors is provided in the form of a mesh connected network which rhythmically compute and pass data through the system. Each processor in the system regularly feeds data in and out, each time performing some computation, so that a regular flow of dat

대표청구항

In a computer system having external handling means delivering input to be processed and receiving output and a plurality of processors forming a network receiving said input, the improvement comprising said plurality of processors being independent of a central control which sends control instructi

이 특허에 인용된 특허 (9)

  1. Chen ; Tien Chi ; Tung ; Chin ; Lum ; Vincent Y., Apparatus for sorting records in overlap relation with record loading and extraction.
  2. Brown Thomas Graham (Aberdour SC) Skrgatic Damir Josip Miroslav (Livingston SC) Younger Graeme William (Newbridge SC) Fortune John Cook (Edinburgh SC), Apparatus for the ultrasonic examination of bodies having non-planar surfaces.
  3. Chen ; Tien Chi ; Eswaran ; Kapali P. ; Lum ; Vincent Yu-Sun ; Tung ; Ch in, Apparatus for transposition sorting of equal length records in overlap relation with record loading and extraction.
  4. Mordwinkin George (Scottdale PA), Digital eddy current apparatus for sensing and analyzing metallurgical characteristics of an electrically conductive mat.
  5. Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI), Information processing system.
  6. Chang Hsu (Yorktown Heights NY) Chen Tien Chi (San Jose CA) Tung Chin (Saratoga CA), Ladder for information processing.
  7. Shibayama Shigeki (Yokohama JPX) Kamimura Tsutomu (Kawasaki JPX), Matrix arithmetic apparatus.
  8. Schomberg Hermann (Tangstedt DT) Heubach Frank (Hamburg DT), Network computer system.
  9. Sternberg Stanley R. (Ann Arbor MI), Parallel partitioned serial neighborhood processors.

이 특허를 인용한 특허 (56)

  1. Dawes Robert L. (Allen TX), Adaptive processing system having an array of individually configurable processing components.
  2. Hogg Tad (Anchorage AK) Huberman Bernardo A. (Palo Alto CA), Adaptive processor array capable of learning variable associations useful in recognizing classes of inputs.
  3. Bocker Richard P. (San Diego CA), Advanced cube processor.
  4. McCanny John V. (County Down IEX) Evans Richard A. (Herefordshire GB2) McWhirter John G. (Worcestershire GB2), Bit-slice digital processor for correlation and convolution.
  5. Barkan Mordecai (Palo Alto CA) Genusov Alex (Haifa ILX) Granski Michael (Haifa CA ILX) Budnik Paul (Los Gatos CA) Retter Refael (Haifa ILX), Cascadable digital filter processor employing moving coefficients.
  6. Marwood Warren (Fairview Park AUX), Cellular floating-point serial pipelined multiplier.
  7. Kao Jinn-Nan,TWX, Compact pipelined matrix multiplier utilizing encoding and shifting circuit configurations.
  8. Morton Steven G. (39 Old Good Hill Rd. Oxford CT 06483), Convolution memory.
  9. Emmons, Daniel R.; Swanson, William E., Cross product calculator with normalized output.
  10. Kobori, Tomoyoshi, DMA transfer device and method.
  11. Huberman Bernardo A. (Palo Alto CA) Keirstead William P. (Stanford CA) Singer Stephanie (New York NY), Detection of motion in the presence of noise.
  12. Ward Jeremy S. (Great Malvern GB2), Digital data processor for matrix-vector multiplication.
  13. McCanny John V. (Belfast GB5) McWhirter John G. (Malvern GB2) Wood Kenneth W. (Newcastle-upon-Tyne GB2), Digital data processor for multiplying data by a coefficient set.
  14. Dierckx Rudolf F. I. (Wilrijk BEX) Sallaerts Daniel (Aarschot BEX) Guebels Pierre-Paul F. (Edegem BEX), Echo canceller using an adaptive finite impulse response filter.
  15. Hammond Steven W. (Schenectady NY), Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements.
  16. Gulley David W. (Sugar Land TX) Van Aken Jerry R. (Sugar Land TX), Graphics floating point coprocessor having matrix capabilities.
  17. Dhanoa, Kulwinder, Hardware architecture and scheduling for high performance and low resource solution for QR decomposition.
  18. Dhanoa, Kulwinder; Fitton, Michael, Hardware architecture and scheduling for high performance solution to cholesky decomposition.
  19. Simonds Robert M. (Mercer Island WA), Image processing using multi-pass convolution with small kernels.
  20. Chen, Chia-Yu; Choi, Jungwook; Gopalakrishnan, Kailash; Han, Victor; Srinivasan, Vijayalakshmi; Zhang, Jintao, Matrix multiplication on a systolic array.
  21. Chen, Chia-Yu; Choi, Jungwook; Gopalakrishnan, Kailash; Han, Victor; Srinivasan, Vijayalakshmi; Zhang, Jintao, Matrix multiplication on a systolic array.
  22. Ruehle, Michael D., Method and apparatus for performing modular multiplication.
  23. Hieftje Gary M. (Bloomington IN) Honigs David H. (Bloomington IN), Method and device for spectral reconstruction.
  24. Doerr, Michael B.; Dobbs, Carl S.; Solka, Michael B.; Trocino, Michael R.; Gibson, David A., Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration.
  25. Grinberg Jan (Los Angeles CA) Yamagishi Frederick G. (Newbury Park CA), Method of performing matrix by matrix multiplication.
  26. Leibowitz Lawrence M. (Fairfax VA), Multiplexed digital correlator.
  27. Barman, Kaushik; Dighe, Parag; Rao, Ragahavendar M., Multiplication of matrices using systolic arrays.
  28. Doerr, Michael B.; Dobbs, Carl S.; Solka, Michael B.; Trocino, Michael R.; Gibson, David A., Multiprocessor fabric having configurable communication that is selectively disabled for secure processing.
  29. Shakamuri, Harish Kumar; Kamath, Ashwin; Enz, Michael, PCIe switch with data and control path systolic array.
  30. Chuang Henry Y. H. (Pittsburgh PA) He Guo (Wuhan CNX), Pipeline feedback array sorter with multi-string sort array and merge tree array.
  31. McCanny John V. (Malvern GB2) McWhirter John G. (Malvern GB2) Wood Kenneth W. (Newcastle-upon-Tyne GB2), Pipelined systolic array for matrix-matrix multiplication.
  32. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved communication routing.
  33. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and communication elements having improved wormhole routing.
  34. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Processing system with interspersed processors and dynamic pathway creation.
  35. Doerr,Michael B.; Hallidy,William H.; Gibson,David A.; Chase,Craig M., Processing system with interspersed stall propagating processors and communication elements.
  36. McWhirter John G. (Malvern Wells GB2) Shepherd Terence J. (Malvern GB2), Processor for constrained least squares computations.
  37. Hsu Yarsun (Pleasantville NY) Li Hungwen (Pleasantville NY), Programmable variable-cycle clock circuit for skew-tolerant array processor architecture.
  38. Beardslee, John Mark; Doerr, Michael B.; Eng, Tommy K., Programming a multi-processor system.
  39. Beardslee, John Mark; Doerr, Michael B.; Eng, Tommy K., Programming a multi-processor system.
  40. Beardslee, John Mark; Doerr, Michael B.; Eng, Tommy K., Programming a multi-processor system.
  41. Arthur, John V.; Barth, Jr., John E.; Merolla, Paul A.; Modha, Dharmendra S., Providing transposable access to a synapse array using a recursive array layout.
  42. Arthur, John V.; Barth, Jr., John E.; Merolla, Paul A.; Modha, Dharmendra S., Providing transposable access to a synapse array using a recursive array layout.
  43. Arthur, John V.; Barth, Jr., John E.; Merolla, Paul A.; Modha, Dharmendra S., Providing transposable access to a synapse array using column aggregation.
  44. Ebeling William Henry Carl ; Cronquist Darren Charles ; Franklin Paul David, Reconfigurable computing architecture for providing pipelined data paths.
  45. Doerr, Michael B.; Dobbs, Carl S.; Solka, Michael B.; Trocino, Michael R.; Gibson, David A., Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric.
  46. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, Sleep mode initialization in a distributed computing system.
  47. Gupta Subhash ; Mehrotra Ravi, Speedup for solution of systems of linear equations.
  48. Doerr, Michael B.; Hallidy, William H.; Gibson, David A.; Chase, Craig M., Stall propagation in a processing system with interspersed processors and communicaton elements.
  49. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.
  50. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.
  51. Chall, Louis Edumund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.
  52. Chang Jaw J. (Arcadia CA) Yeh Hen-Geul (Lomita CA), Systolic VLSI array for implementing the Kalman filter algorithm.
  53. Seki, Katsutoshi, Systolic array.
  54. Khan Emdadur R. (San Jose CA), Systolic array for multidimensional matrix computations.
  55. Parvin Bahram A. (Fountain Valley CA), Systolic array for solving cyclic loop dependent algorithms.
  56. Helbig ; Sr. Walter A. (Medford Lakes NJ), Systolic array processing apparatus.
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