$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Dielectrically isolated semiconductor devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/306
  • H01L-021/76
출원번호 US-0460399 (1983-01-24)
발명자 / 주소
  • Frye Robert C. (Piscataway NJ) Griffith Joseph E. (New Providence NJ) Wong Yiu H. (Berkeley Heights NJ)
출원인 / 주소
  • AT&T Bell Laboratories (Murray Hill NJ 02)
인용정보 피인용 횟수 : 27  인용 특허 : 4

초록

Dielectrically isolated single crystal silicon of high quality is produced by an extremely convenient process. This process involves the fusing of two silicon bodies where at least one of these bodies has a region of silicon oxide. The bodies are contacted so that the silicon oxide is at an interfac

대표청구항

A process for producing a dielectrically isolated silicon region comprising the steps of (1) contacting a first and second body so that a silicon oxide and OH moieties are present at the interface between said first and second body and fusing said first and second bodies, wherein said fusion is acco

이 특허에 인용된 특허 (4)

  1. Wallis ; George, Application of field-assisted bonding to the mass production of silicon type pressure transducers.
  2. Allison David F. (Palo Alto CA) Maxwell David A. (San Jose CA), Method for making semiconductor structure.
  3. Riseman Jacob (Poughkeepsie NY), Method of forming an integrated circuit structure with fully-enclosed air isolation.
  4. Suzuki Takaya (Hitachi JA) Mimura Akio (Hitachi JA) Yagyu Seturo (Hitachi JA) Okuhara Shinji (Fujisawa JA), Method of manufacturing semiconductor integrated circuit with prevention of substrate warpage.

이 특허를 인용한 특허 (27)

  1. Iida Makio,JPX ; Saitou Mitsuhiro,JPX ; Murata Akitaka,JPX ; Ban Hiroyuki,JPX ; Suzuki Tadashi,JPX ; Sakakibara Toshio,JPX ; Sugisaka Takayuki,JPX ; Miura Shoji,JPX, Design for a semiconductor device having elements isolated by insulating regions.
  2. Short John P. (Indian Harbour Beach FL) Rouse George V. (Melbourne FL), Dielectric isolation process using double wafer bonding.
  3. Adler Michael S. (Schenectady NY), Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices.
  4. Usenko, Alex, Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof.
  5. Peidous, Igor; Kommu, Srikanth; Wang, Gang; Thomas, Shawn George, High resistivity SOI wafers and a method of manufacturing thereof.
  6. Liu, Qingmin; Standley, Robert Wendell, High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation.
  7. Hu Chenming (Alamo CA) Sapp Steven P. (Felton CA), High voltage power IC process.
  8. Alexander Elizabeth M. L. (Eindhoven NLX) Haisma Jan (Eindhoven NLX) Michielsen Theodorus (Eindhoven NLX) Van Der Velden Johannes (Eindhoven NLX) Verhoeven Johannes F. C. M. (Eindhoven NLX), Improved method of manufacturing a semiconductor device of the “semiconductor on insulator”type.
  9. Kitahara Koichi (Kawasaki JPX) Ohata Yu (Tokyo JPX) Kuramoto Tsuyoshi (Yokohama JPX), Manufacture of a substrate structure for a composite semiconductor device using wafer bonding and epitaxial refill.
  10. Butt Sheldon H. (Godfrey IL) Mahulikar Deepak (Meriden CT), Metal packages having improved thermal dissipation.
  11. Flesner, Larry D.; Garcia, Graham A.; Imthurn, George P., Method for fabricating a silicon-on-insulator voltage multiplier.
  12. Richardson William E. (Rutland MA), Method for making IC die with dielectric isolation.
  13. Ueda, Nobumasa; Mizuno, Shoji, Method for manufacturing semiconductor device having element isolation structure.
  14. Blanchard Richard A. (Los Altos CA), Method for providing dielectrically isolated circuit.
  15. Hsu, Shu-Ya, Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation.
  16. Shimbo Masaru (Yokohama JPX) Fukuda Kiyoshi (Yokohama JPX), Method of bonding crystalline silicon bodies.
  17. Sawada Renshi (Tokorozawa JPX) Watanabe Junji (Tokyo JPX), Method of joining semiconductor substrates.
  18. Haisma Jan (Eindhoven NLX) Alting Cornelis L. (Eindhoven NLX) Michielsen Theodorus M. (Eindhoven NLX), Method of manufacturing a semiconductor device.
  19. Yamaki Bunshiro (Fujisawa JPX) Matsuoka Nobutaka (Yokohama JPX), Method of manufacturing from a semiconductor wafer a dielectric substrate including mutually insulated and separated isl.
  20. Thomas, Shawn George; Liu, Qingmin, Method of manufacturing high resistivity silicon-on-insulator substrate.
  21. Shimbo Masaru (Yokohama JPX) Fukuda Kiyoshi (Yokohama JPX) Ohwada Yoshiaki (Yokohama JPX), Method of manufacturing semiconductor substrate.
  22. Peidous, Igor; Jones, Andrew M.; Kommu, Srikanth; Libbert, Jeffrey L., Process flow for manufacturing semiconductor on insulator structures in parallel.
  23. Kubo Takashi (Kaisei JPX), Process for producing multilayer conductor structure.
  24. Ueda, Nobumasa; Mizuno, Shoji, Semiconductor device having element isolation structure.
  25. Moslehi, Mehrdad M., Soi wafer fabrication by selective epitaxial growth.
  26. Ohkubo, Yasunori, Substrate having a semiconductor layer, and method for fabricating the same.
  27. Kitahara Koichi (Kawasaki JPX) Natsume Yoshinori (Hyogo JPX) Hosoki Yoshinori (Kawasaki JPX), Substrate structure for composite semiconductor device.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로